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gpl-2.0

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

eda spef vlsi gdsii parse interconnect vlsi-circuits integrated-circuits electronic-design-automation

Created 2018-10-05

233 commits to master branch, last one about a year ago

mit

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

eda sta spef vlsi cpp17 circuits parasitic vlsi-circuits vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation

Created 2018-08-08

215 commits to master branch, last one 2 years ago