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47

A High-performance Timing Analysis Tool for VLSI Systems

cad eda sta vlsi cpp17 verilog vlsi-circuits circuit-analysis circuit-simulator circuit-simulation parallel-computing vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation

Created 2015-07-14

216 commits to master branch, last one about a year ago

32

130

apache-2.0

14

Standard Cell Library based Memory Compiler using FF/Latch cells

vlsi verilog asic-design vlsi-circuits electronics-design vlsi-physical-design

Created 2020-11-09

281 commits to main branch, last one 8 months ago

18

111

gpl-2.0

10

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

eda spef vlsi gdsii parse interconnect vlsi-circuits integrated-circuits electronic-design-automation

Created 2018-10-05

233 commits to master branch, last one about a year ago

33

79

mit

8

A Standalone Structural Verilog Parser

eda flex cpp17 circuit verilog bison-yacc vlsi-circuits vlsi-physical-design computer-aided-design electronic-design-automation

Created 2019-01-04

67 commits to master branch, last one 3 years ago

19

50

mit

7

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

eda sta spef vlsi cpp17 circuits parasitic vlsi-circuits vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation

Created 2018-08-08

215 commits to master branch, last one 2 years ago