OpenTimer / Parser-Verilog

A Standalone Structural Verilog Parser

Date Created 2019-01-04 (6 years ago)
Commits 67 (last one 3 years ago)
Stargazers 89 (2 this week)
Watchers 7 (0 this week)
Forks 35
License mit
Ranking

RepositoryStats indexes 624,936 repositories, of these OpenTimer/Parser-Verilog is ranked #329,064 (47th percentile) for total stargazers, and #260,024 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #270/609.

OpenTimer/Parser-Verilog is also tagged with popular topics, for these it's ranked: verilog (#184/304),  eda (#96/146)

Other Information

OpenTimer/Parser-Verilog has 5 open pull requests on Github, 2 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 6 open issues and 2 closed issues.

Star History

Github stargazers over time

90908080707060605050404030302020101000202020202021202120222022202320232024202420252025

Watcher History

Github watchers over time, collection started in '23

8888887.57.577777720232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Recent Commit History

0 commits on the default branch (master) since jan '22

Inactive

No recent commits to this repository

Yearly Commits

Commits to the default branch (master) per year

7070606050504040303020201010002019201920202020202120212022202220242024

Issue History

Total Issues
Open Issues
Closed Issues
887766554433221100202020202021202120222022202320232024202420252025

Languages

The primary language is Verilog but there's also others...

VerilogVerilogC++C++YaccYaccLexLexCMakeCMake

updated: 2025-03-07 @ 07:45pm, id: 164126589 / R_kgDOCchffQ