10 results found Sort:

limbo018
DREAMPlace limbo018
208
726
bsd-3-clause
22
Deep learning toolkit-enabled VLSI placement
vlsi pytorch deep-learning vlsi-placement gpu-acceleration vlsi-physical-design
Created 2019-02-28
761 commits to master branch, last one about a month ago
OpenTimer
OpenTimer OpenTimer
144
577
other
48
A High-performance Timing Analysis Tool for VLSI Systems
cad eda sta vlsi cpp17 verilog vlsi-circuits circuit-analysis circuit-simulator circuit-simulation parallel-computing vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation
Created 2015-07-14
216 commits to master branch, last one 2 years ago
AUCOHL
DFFRAM AUCOHL
33
137
apache-2.0
14
Standard Cell Library based Memory Compiler using FF/Latch cells
vlsi verilog asic-design vlsi-circuits electronics-design vlsi-physical-design
Created 2020-11-09
281 commits to main branch, last one 11 months ago
cuhk-eda
dr-cu cuhk-eda
36
130
other
9
Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
eda routing vlsi-physical-design
Created 2019-05-07
33 commits to master branch, last one 3 years ago
OpenTimer
Parser-Verilog OpenTimer
34
86
mit
8
A Standalone Structural Verilog Parser
eda flex cpp17 circuit verilog bison-yacc vlsi-circuits vlsi-physical-design computer-aided-design electronic-design-automation
Created 2019-01-04
67 commits to master branch, last one 3 years ago
lip6
coriolis lip6
10
58
gpl-2.0
12
Coriolis VLSI EDA Tool (LIP6)
eda vlsi-physical-design
Created 2023-07-13
3,431 commits to main branch, last one 2 months ago
OpenTimer
Parser-SPEF OpenTimer
21
53
mit
8
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
eda sta spef vlsi cpp17 circuits parasitic vlsi-circuits vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation
Created 2018-08-08
215 commits to master branch, last one 2 years ago
AngeloJacobo
OpenLANE-Sky130-Physical-Design-Workshop AngeloJacobo
15
51
mit
2
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
asic vlsi sky130 rtl2gds openlane openlane-flow vlsi-physical-design
Created 2022-08-04
150 commits to main branch, last one 2 years ago
twweeb
VLSI-Physical-Design-Automation twweeb
8
41
unknown
2
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
eda nthu vlsi vlsi-cad vlsi-design vlsi-routing fixed-outline global-routing vlsi-floorplan vlsi-placement two-way-min-cut global-placement vlsi-physical-design physical-design-automation
Created 2020-11-05
29 commits to master branch, last one 3 years ago
shariethernet
Physical-Design-with-OpenLANE-using-SKY130-PDK shariethernet
7
37
unknown
2
This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII F...
risc-v vlsi-physical-design electronics-engineering
Created 2021-06-29
56 commits to main branch, last one 3 years ago