AUCOHL / DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

Date Created 2020-11-09 (4 years ago)

Commits 281 (last one about a year ago)

Stargazers 143 (0 this week)

Watchers 13 (0 this week)

Forks 33

License apache-2.0

Ranking

RepositoryStats indexes 624,936 repositories, of these AUCOHL/DFFRAM is ranked #237,330 (62nd percentile) for total stargazers, and #161,073 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #169/609.

AUCOHL/DFFRAM is also tagged with popular topics, for these it's ranked: verilog (#128/304)

Other Information

AUCOHL/DFFRAM has 4 open pull requests on Github, 92 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 28 open issues and 54 closed issues.

There have been 6 releases, the latest one was published on 2024-01-07 (about a year ago)

All Topics

vlsi verilog asic-design vlsi-circuits electronics-design vlsi-physical-design

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

46 commits on the default branch (main) since jan '22

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2025-03-07 @ 12:34am, id: 311306901 / R_kgDOEo4qlQ