shariethernet / Physical-Design-with-OpenLANE-using-SKY130-PDK

This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisations are carried out. Slack violations are removed. DRC is verified

shariethernet
shariethernet
Date Created 2021-06-29 (3 years ago)
Commits 56 (last one 3 years ago)
Stargazers 37 (0 this week)
Watchers 2 (0 this week)
Forks 8
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RepositoryStats indexes 589,134 repositories, of these shariethernet/Physical-Design-with-OpenLANE-using-SKY130-PDK is ranked #530,745 (10th percentile) for total stargazers, and #481,361 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #488/549.

shariethernet/Physical-Design-with-OpenLANE-using-SKY130-PDK is also tagged with popular topics, for these it's ranked: risc-v (#245/265)

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updated: 2024-11-07 @ 02:48pm, id: 381450472 / R_kgDOFrx46A