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147

mit

Library for VLSI CAD Design Useful parsers and solvers' api are implemented.

cad eda parsers solvers vlsi-design

Created 2017-10-14

638 commits to master branch, last one about a year ago

unknown

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

fpga risc-v vlsi-design digital-design system-on-chip embedded-systems computer-architecture

Created 2024-02-19

40 commits to main branch, last one 2 months ago

apache-2.0

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

asic fpga verilog-hdl vlsi-design xilinx-vivado digital-system-design

Created 2023-03-26

180 commits to main branch, last one about a year ago

unknown

Courseworks of CS6165 VLSI Physical Design Automation, NTHU.

eda nthu vlsi vlsi-cad vlsi-design vlsi-routing fixed-outline global-routing vlsi-floorplan vlsi-placement two-way-min-cut global-placement vlsi-physical-design physical-design-automation

Created 2020-11-05

29 commits to master branch, last one 3 years ago