Search Results - RepositoryStats

50

149

mit

11

Library for VLSI CAD Design Useful parsers and solvers' api are implemented.

cad eda parsers solvers vlsi-design

Created 2017-10-14

638 commits to master branch, last one about a year ago

4

74

unknown

7

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

fpga risc-v vlsi-design digital-design system-on-chip embedded-systems computer-architecture

Created 2024-02-19

40 commits to main branch, last one 3 months ago

12

59

apache-2.0

3

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

asic fpga verilog-hdl vlsi-design xilinx-vivado digital-system-design

Created 2023-03-26

180 commits to main branch, last one about a year ago

8

41

unknown

2

Courseworks of CS6165 VLSI Physical Design Automation, NTHU.

eda nthu vlsi vlsi-cad vlsi-design vlsi-routing fixed-outline global-routing vlsi-floorplan vlsi-placement two-way-min-cut global-placement vlsi-physical-design physical-design-automation

Created 2020-11-05

29 commits to master branch, last one 3 years ago

6

35

mpl-2.0

2

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

rtl vlsi verilog wallace fulladder dadda-tree multiplier vlsi-design vlsi-project carry-save-adder dadda-multiplier tree-multipliers fast-multiplication hardware-description-language

Created 2021-04-19

10 commits to main branch, last one 6 months ago