ekb0412 / 100DaysofRTL

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

ekb0412
ekb0412
Date Created 2023-03-26 (2 years ago)
Commits 180 (last one about a year ago)
Stargazers 67 (0 this week)
Watchers 3 (0 this week)
Forks 13
License apache-2.0
Ranking

RepositoryStats indexes 631,351 repositories, of these ekb0412/100DaysofRTL is ranked #402,436 (36th percentile) for total stargazers, and #417,031 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #337/617.

ekb0412/100DaysofRTL is also tagged with popular topics, for these it's ranked: fpga (#358/515)

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

180 commits on the default branch (main) since jan '22

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Yearly Commits

Commits to the default branch (main) per year

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Issue History

No issues have been posted

Languages

The only known language in this repository is Verilog

VerilogVerilog

updated: 2025-03-07 @ 06:57pm, id: 619108844 / R_kgDOJObZ7A