ekb0412 / 100DaysofRTL

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

Date Created 2023-03-26 (about a year ago)

Commits 180 (last one about a year ago)

Stargazers 52 (0 this week)

Watchers 3 (0 this week)

Forks 11

License apache-2.0

Ranking

RepositoryStats indexes 579,555 repositories, of these ekb0412/100DaysofRTL is ranked #447,639 (23rd percentile) for total stargazers, and #420,420 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #386/533.

ekb0412/100DaysofRTL is also tagged with popular topics, for these it's ranked: fpga (#387/475)

All Topics

asic fpga verilog-hdl vlsi-design xilinx-vivado digital-system-design

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

180 commits on the default branch (main) since jan '22

Yearly Commits

Commits to the default branch (main) per year

Issue History

No issues have been posted

Languages

The only known language in this repository is Verilog

updated: 2024-11-05 @ 03:02pm, id: 619108844 / R_kgDOJObZ7A