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ekb0412
100DaysofRTL ekb0412
11
52
apache-2.0
3
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
asic fpga verilog-hdl vlsi-design xilinx-vivado digital-system-design
Created 2023-03-26
180 commits to main branch, last one about a year ago
hadis98
IUT hadis98
2
30
unknown
4
All my projects, homework, hand writings, course slides and anything I have learned and done during my study in IUT university😊. feel free to give it a ⭐=)
proteus algorithms codevision network-lab architecutre database-lab microprocessor automata-theory compiler-design data-structures basic-programming computer-networks operating-systems signals-and-systems advanced-programming digital-system-design
Created 2022-11-24
75 commits to main branch, last one 10 months ago