meiniKi / FazyRV

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

Date Created 2024-02-19 (3 months ago)

Commits 33 (last one 16 days ago)

Stargazers 60 (0 this week)

Watchers 7 (0 this week)

Forks 1

License unknown

Ranking

RepositoryStats indexes 523,840 repositories, of these meiniKi/FazyRV is ranked #376,964 (28th percentile) for total stargazers, and #256,773 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #98/152.

meiniKi/FazyRV is also tagged with popular topics, for these it's ranked: fpga (#326/425), risc-v (#162/221), embedded-systems (#143/181)

All Topics

fpga risc-v vlsi-design digital-design system-on-chip embedded-systems computer-architecture

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

33 commits on the default branch (main) since jan '22

Yearly Commits

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Issue History

No issues have been posted

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-05-16 @ 12:53pm, id: 760114130 / R_kgDOLU5r0g