tharunchitipolu / Dadda-Multiplier-using-CSA

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

Date Created 2021-04-19 (3 years ago)

Commits 10 (last one 6 months ago)

Stargazers 36 (0 this week)

Watchers 2 (0 this week)

Forks 6

License mpl-2.0

Ranking

RepositoryStats indexes 595,856 repositories, of these tharunchitipolu/Dadda-Multiplier-using-CSA is ranked #540,805 (9th percentile) for total stargazers, and #485,301 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #505/563.

tharunchitipolu/Dadda-Multiplier-using-CSA is also tagged with popular topics, for these it's ranked: verilog (#274/289)

All Topics

rtl vlsi verilog wallace fulladder dadda-tree multiplier vlsi-design vlsi-project carry-save-adder dadda-multiplier tree-multipliers fast-multiplication hardware-description-language

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Recent Commit History

4 commits on the default branch (main) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2024-12-22 @ 03:10am, id: 359409118 / R_kgDOFWwl3g