tharunchitipolu / Dadda-Multiplier-using-CSA

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

tharunchitipolu
tharunchitipolu
Date Created 2021-04-19 (3 years ago)
Commits 10 (last one 9 months ago)
Stargazers 34 (0 this week)
Watchers 1 (0 this week)
Forks 6
License mpl-2.0
Ranking

RepositoryStats indexes 628,089 repositories, of these tharunchitipolu/Dadda-Multiplier-using-CSA is ranked #576,505 (8th percentile) for total stargazers, and #554,057 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #552/609.

tharunchitipolu/Dadda-Multiplier-using-CSA is also tagged with popular topics, for these it's ranked: verilog (#289/305)

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

4 commits on the default branch (main) since jan '22

443.53.5332.52.5221.51.5110.50.500Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (main) per year

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Issue History

Total Issues
Open Issues
Closed Issues
1111110.50.5000000Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Languages

The primary language is Verilog but there's also others...

VerilogVerilogCoqCoq

updated: 2025-03-07 @ 09:33am, id: 359409118 / R_kgDOFWwl3g