4 results found Sort:

25
177
bsd-3-clause
18
A Chisel RTL generator for network-on-chip interconnects
Created 2021-10-04
411 commits to master branch, last one 13 days ago
An AXI4 crossbar implementation in SystemVerilog
Created 2021-09-23
57 commits to main branch, last one 7 days ago
19
116
gpl-2.0
10
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
Created 2018-10-05
233 commits to master branch, last one about a year ago
AHB3-Lite Interconnect
Created 2017-03-29
145 commits to master branch, last one 6 months ago