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Open-source high-performance RISC-V processor
Created
2020-06-13
9,226 commits to master branch, last one 14 hours ago
Chisel: A Modern Hardware Design Language
Created
2015-04-27
5,921 commits to main branch, last one 13 hours ago
Rocket Chip Generator
Created
2014-09-12
8,667 commits to master branch, last one 2 months ago
SonicBOOM: The Berkeley Out-of-Order Machine
Created
2014-01-21
2,320 commits to master branch, last one 14 days ago
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Created
2016-10-24
4,613 commits to main branch, last one a day ago
Simple RISC-V 3-stage Pipeline in Chisel
Created
2016-09-28
222 commits to main branch, last one 2 months ago
Work in progress prototype for the Chisel Level Editor, for Unity
Created
2019-02-05
393 commits to master branch, last one about a year ago
A .NET XOR encrypted cobalt strike aggressor implementation for chisel to utilize faster proxy and advanced socks5 capabilities.
Created
2022-07-10
6 commits to main branch, last one 2 months ago
The batteries-included testing and formal verification library for Chisel-based RTL designs.
Created
2018-08-24
404 commits to main branch, last one about a month ago
Establish a Reverse Tunnel between different servers and clients. IPV4 | IPV6 - Supports TCP & UDP . You can establish a tunnel between 5 Kharej servers & 1 IRAN server and vice versa.
Created
2023-12-01
106 commits to main branch, last one 3 months ago
A compact guide to network pivoting for penetration testings / CTF challenges.
Created
2022-02-12
57 commits to main branch, last one about a year ago
All-in-one OPIran scripts
Created
2023-12-01
111 commits to main branch, last one 3 months ago
Support files for participating in a Fomu workshop
Created
2019-08-16
661 commits to master branch, last one 2 months ago
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
Created
2020-01-21
325 commits to master branch, last one 2 years ago
A Chisel RTL generator for network-on-chip interconnects
Created
2021-10-04
406 commits to master branch, last one 3 months ago
A dynamic verification library for Chisel.
Created
2020-05-27
229 commits to master branch, last one 8 days ago
high-performance RTL simulator
Created
2019-10-17
891 commits to master branch, last one about a month ago
Provides dot visualizations of chisel/firrtl circuits
Created
2018-10-31
115 commits to master branch, last one 2 years ago
Chisel components for FPGA projects
Created
2015-06-25
601 commits to master branch, last one 8 months ago
(System)Verilog to Chisel translator
Created
2020-08-26
110 commits to master branch, last one 2 years ago
A RISC-V Core (RV32I) written in Chisel HDL
Created
2021-09-27
313 commits to main branch, last one 4 months ago
Establishing a Direct tunnel using chisel between Servers and Client - IPV4 | IPV6 - TCP | UDP - [5] Kharej [1] IRAN
Created
2024-01-19
27 commits to main branch, last one 3 months ago
Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
This repository has been archived
(exclude archived)
Created
2021-01-14
50 commits to main branch, last one about a year ago
Kubernetes Operator for Chisel
Created
2023-05-11
188 commits to main branch, last one about a month ago
lldb命令-symbolic
Created
2018-12-15
7 commits to master branch, last one 3 years ago
Learning how to make RISC-V 32bit CPU with Chisel
Created
2021-08-22
67 commits to main branch, last one 2 years ago
FFT generator using Chisel
Created
2020-04-30
20 commits to master branch, last one 2 years ago
🛠 lldb, breakpoint, shortcut 등을 이용한 생산성 향상 방법을 배워보자 🛠
Created
2021-09-16
27 commits to main branch, last one 2 years ago
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Created
2020-04-08
740 commits to master branch, last one 3 years ago
Personal CheatSheet used for the exam made with Obsidian, download the repo and use the resources within Obsidian for a better experience. CHISEL & SOCAT BINARIES ARE WITHIN THE PIVOTING SECTION.
Created
2023-02-06
10 commits to main branch, last one about a year ago