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XiangShan OpenXiangShan

608

4.4k

other

92

Open-source high-performance RISC-V processor

chisel risc-v microarchitecture

Created 2020-06-13

9,226 commits to master branch, last one 14 hours ago

chisel chipsalliance

574

3.8k

apache-2.0

148

Chisel: A Modern Hardware Design Language

rtl scala chisel firrtl chisel3 verilog chip-generator

Created 2015-04-27

5,921 commits to main branch, last one 13 hours ago

rocket-chip chipsalliance

1.1k

3.0k

other

197

Rocket Chip Generator

rtl riscv scala chisel rocket-chip chip-generator

Created 2014-09-12

8,667 commits to master branch, last one 2 months ago

riscv-boom riscv-boom

405

1.6k

bsd-3-clause

84

SonicBOOM: The Berkeley Out-of-Order Machine

rtl boom riscv scala chisel berkeley riscv-boom rocket-chip

Created 2014-01-21

2,320 commits to master branch, last one 14 days ago

chipyard ucb-bar

598

1.5k

bsd-3-clause

82

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

rtl soc boom riscv chisel hwacha risc-v rocket firesim chipyard peripherals rocket-chip superscalar accelerators out-of-order chip-generator

Created 2016-10-24

4,613 commits to main branch, last one a day ago

riscv-mini ucb-bar

100

504

other

39

Simple RISC-V 3-stage Pipeline in Chisel

rtl riscv chisel

Created 2016-09-28

222 commits to main branch, last one 2 months ago

Chisel.Prototype RadicalCSG

33

460

mit

35

Work in progress prototype for the Chisel Level Editor, for Unity

bsp csg unity chisel mapping realtime prototype leveldesign level-design level-editor constructive-solid-geometry

Created 2019-02-05

393 commits to master branch, last one about a year ago

Chisel-Strike m3rcer

57

424

gpl-3.0

8

A .NET XOR encrypted cobalt strike aggressor implementation for chisel to utilize faster proxy and advanced socks5 capabilities.

chisel socks5 redteaming cobalt-strike aggressor-scripts

Created 2022-07-10

6 commits to main branch, last one 2 months ago

chiseltest ucb-bar

70

208

other

25

The batteries-included testing and formal verification library for Chisel-based RTL designs.

chisel formal testing verification

Created 2018-08-24

404 commits to main branch, last one about a month ago

Chisel_multipleServers Azumi67

41

201

gpl-3.0

1

Establish a Reverse Tunnel between different servers and clients. IPV4 | IPV6 - Supports TCP & UDP . You can establish a tunnel between 5 Kharej servers & 1 IRAN server and vice versa.

tcp udp azumi v2ray chisel tunnel openvpn wireguard reverse-tunnel

Created 2023-12-01

106 commits to main branch, last one 3 months ago

pentest-pivoting t3l3machus

39

175

unknown

3

A compact guide to network pivoting for penetration testings / CTF challenges.

ssh proxy chisel socks4 socks5 hacking network pivoting sshuttle burpsuite pentesting proxychains double-pivoting

Created 2022-02-12

57 commits to main branch, last one about a year ago

pf-tun opiran-club

42

163

gpl-3.0

3

All-in-one OPIran scripts

frp 6to4 bbrv3 socat chisel iptables optimizer softether tunneling private-ip ssh-tunnel tunnelbroker

Created 2023-12-01

111 commits to main branch, last one 3 months ago

fomu-workshop im-tomu

63

157

apache-2.0

12

Support files for participating in a Fomu workshop

hdl fomu fpga vhdl litex migen riscv chisel verilog fomu-workshop

Created 2019-08-16

661 commits to master branch, last one 2 months ago

Fuxi MaxXSoft

20

150

gpl-3.0

4

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

cpu fpga riscv scala chisel

Created 2020-01-21

325 commits to master branch, last one 2 years ago

constellation ucb-bar

21

149

bsd-3-clause

17

A Chisel RTL generator for network-on-chip interconnects

noc rtl soc chisel hardware interconnect network-on-chip

Created 2021-10-04

406 commits to master branch, last one 3 months ago

chiselverify chiselverify

21

134

bsd-2-clause

12

A dynamic verification library for Chisel.

scala chisel testing coverage chisel-test verification timed-assertions functional-coverage bus-functional-model constrained-random-verification

Created 2020-05-27

229 commits to master branch, last one 8 days ago

essent ucsc-vama

11

116

other

8

high-performance RTL simulator

rtl scala chisel firrtl

Created 2019-10-17

891 commits to master branch, last one about a month ago

diagrammer freechipsproject

20

112

apache-2.0

17

Provides dot visualizations of chisel/firrtl circuits

chisel firrtl chisel3 visualization

Created 2018-10-31

115 commits to master branch, last one 2 years ago

fpga-tidbits maltanar

27

111

bsd-2-clause

10

Chisel components for FPGA projects

fpga chisel hardware-libraries

Created 2015-06-25

601 commits to master branch, last one 8 months ago

sv2chisel ovh

10

98

bsd-3-clause

18

(System)Verilog to Chisel translator

eda chisel verilog transpiler

Created 2020-08-26

110 commits to master branch, last one 2 years ago

chiselv carlosedp

16

95

mit

6

A RISC-V Core (RV32I) written in Chisel HDL

core fpga riscv chisel risc-v

Created 2021-09-27

313 commits to main branch, last one 4 months ago

Direct_Chisel Azumi67

23

70

mit

1

Establishing a Direct tunnel using chisel between Servers and Client - IPV4 | IPV6 - TCP | UDP - [5] Kharej [1] IRAN

tcp udp v2ray chisel tunnel openvpn wireguard

Created 2024-01-19

27 commits to main branch, last one 3 months ago

chisel-circt sifive

9

69

apache-2.0

18

Library to compile Chisel circuits using LLVM/MLIR (CIRCT)

mlir circt scala chisel

This repository has been archived (exclude archived)

Created 2021-01-14

50 commits to main branch, last one about a year ago

chisel-operator FyraLabs

6

63

gpl-3.0

2

Kubernetes Operator for Chisel

k8s chisel inlets tunnel inletsdev tunneling inlets-pro kubernetes k8s-operator kubernetes-operator

Created 2023-05-11

188 commits to main branch, last one about a month ago

lldb-symbolic luoqisheng

6

60

mit

2

lldb命令-symbolic

lldb chisel custom-commend

Created 2018-12-15

7 commits to master branch, last one 3 years ago

riscv32-cpu-chisel rhysd

3

53

mit

4

Learning how to make RISC-V 32bit CPU with Chisel

cpu chisel risc-v chisel3

Created 2021-08-22

67 commits to main branch, last one 2 years ago

Chisel-FFT-generator IA-C-Lab-Fudan

16

52

unknown

2

FFT generator using Chisel

fft chisel rtl-generator

Created 2020-04-30

20 commits to master branch, last one 2 years ago

Improving_Productivity sujinnaljin

0

49

unknown

2

🛠 lldb, breakpoint, shortcut 등을 이용한 생산성 향상 방법을 배워보자 🛠

lldb xcode chisel debugging shortcuts

Created 2021-09-16

27 commits to main branch, last one 2 years ago

KyogenRV panda5mt

4

42

apache-2.0

3

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

fpga intel riscv rv32i altera chisel risc-v chisel3 avalon-mm

Created 2020-04-08

740 commits to master branch, last one 3 years ago

eCPPTv2-Personal-Cheatsheet-ESP- sergiovks

6

40

cc0-1.0

1

Personal CheatSheet used for the exam made with Obsidian, download the repo and use the resources within Obsidian for a better experience. CHISEL & SOCAT BINARIES ARE WITHIN THE PIVOTING SECTION.

lab ecppt notes socat chisel ecpptv2 pivoting cheatsheet ecpptv2-notes

Created 2023-02-06

10 commits to main branch, last one about a year ago