Search Results - RepositoryStats

XiangShan OpenXiangShan

664

4.9k

other

86

Open-source high-performance RISC-V processor

chisel risc-v microarchitecture

Created 2020-06-13

10,311 commits to master branch, last one 24 hours ago

chisel chipsalliance

599

4.0k

apache-2.0

150

Chisel: A Modern Hardware Design Language

rtl scala chisel firrtl chisel3 verilog chip-generator

Created 2015-04-27

6,172 commits to main branch, last one 20 hours ago

rocket-chip chipsalliance

1.1k

3.3k

other

197

Rocket Chip Generator

rtl riscv scala chisel rocket-chip chip-generator

Created 2014-09-12

8,973 commits to master branch, last one 9 days ago

riscv-boom riscv-boom

426

1.7k

bsd-3-clause

87

SonicBOOM: The Berkeley Out-of-Order Machine

rtl boom riscv scala chisel berkeley riscv-boom rocket-chip

Created 2014-01-21

2,345 commits to master branch, last one about a month ago

chipyard ucb-bar

655

1.7k

bsd-3-clause

87

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

rtl soc boom riscv chisel hwacha risc-v rocket firesim chipyard peripherals rocket-chip superscalar accelerators out-of-order chip-generator

Created 2016-10-24

4,982 commits to main branch, last one 12 hours ago

riscv-mini ucb-bar

110

544

other

37

Simple RISC-V 3-stage Pipeline in Chisel

rtl riscv chisel

This repository has been archived (exclude archived)

Created 2016-09-28

223 commits to main branch, last one 5 months ago

Chisel.Prototype RadicalCSG

33

496

mit

31

Work in progress prototype for the Chisel Level Editor, for Unity

bsp csg unity chisel mapping realtime prototype leveldesign level-design level-editor constructive-solid-geometry

This repository has been archived (exclude archived)

Created 2019-02-05

408 commits to master branch, last one about a month ago

Chisel-Strike m3rcer

57

441

gpl-3.0

8

A .NET XOR encrypted cobalt strike aggressor implementation for chisel to utilize faster proxy and advanced socks5 capabilities.

chisel socks5 redteaming cobalt-strike aggressor-scripts

Created 2022-07-10

6 commits to main branch, last one 8 months ago

RISC-V-Single-Cycle-CPU T-K-233

44

425

mit

10

RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

chisel risc-v logisim verilog

Created 2020-04-17

46 commits to main branch, last one 4 months ago

pf-tun opiran-club

60

232

gpl-3.0

3

All-in-one OPIran scripts

frp 6to4 bbrv3 socat chisel iptables optimizer softether tunneling private-ip ssh-tunnel tunnelbroker

Created 2023-12-01

112 commits to main branch, last one 4 months ago

Chisel_multipleServers Azumi67

43

228

gpl-3.0

1

Establish a Reverse Tunnel between different servers and clients. IPV4 | IPV6 - Supports TCP & UDP . You can establish a tunnel between 5 Kharej servers & 1 IRAN server and vice versa.

tcp udp azumi v2ray chisel tunnel openvpn wireguard reverse-tunnel

Created 2023-12-01

110 commits to main branch, last one 5 months ago

chiseltest ucb-bar

74

223

other

23

The batteries-included testing and formal verification library for Chisel-based RTL designs.

chisel formal testing verification

This repository has been archived (exclude archived)

Created 2018-08-24

406 commits to main branch, last one 3 months ago

raster-i alanjian85

7

202

mit

3

A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.

gpu fpga chisel vitis-hls rasterizer tiled-deferred

Created 2023-01-24

230 commits to main branch, last one about a month ago

pentest-pivoting t3l3machus

42

191

unknown

3

A compact guide to network pivoting for penetration testings / CTF challenges.

ssh proxy chisel socks4 socks5 hacking network pivoting sshuttle burpsuite pentesting proxychains double-pivoting

Created 2022-02-12

57 commits to main branch, last one 2 years ago

constellation ucb-bar

25

177

bsd-3-clause

18

A Chisel RTL generator for network-on-chip interconnects

noc rtl soc chisel hardware interconnect network-on-chip

Created 2021-10-04

411 commits to master branch, last one a day ago

fomu-workshop im-tomu

64

162

apache-2.0

13

Support files for participating in a Fomu workshop

hdl fomu fpga vhdl litex migen riscv chisel verilog fomu-workshop

Created 2019-08-16

661 commits to master branch, last one 8 months ago

Fuxi MaxXSoft

22

162

gpl-3.0

5

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

cpu fpga riscv scala chisel

Created 2020-01-21

325 commits to master branch, last one 3 years ago

chiselverify chiselverify

23

142

bsd-2-clause

12

A dynamic verification library for Chisel.

scala chisel testing coverage chisel-test verification timed-assertions functional-coverage bus-functional-model constrained-random-verification

Created 2020-05-27

233 commits to master branch, last one 11 days ago

essent ucsc-vama

13

140

other

8

high-performance RTL simulator

rtl scala chisel firrtl

Created 2019-10-17

891 commits to master branch, last one 7 months ago

fpga-tidbits maltanar

28

119

bsd-2-clause

10

Chisel components for FPGA projects

fpga chisel hardware-libraries

Created 2015-06-25

601 commits to master branch, last one about a year ago

diagrammer freechipsproject

20

115

apache-2.0

17

Provides dot visualizations of chisel/firrtl circuits

chisel firrtl chisel3 visualization

Created 2018-10-31

115 commits to master branch, last one 2 years ago

sv2chisel ovh

10

106

bsd-3-clause

18

(System)Verilog to Chisel translator

eda chisel verilog transpiler

Created 2020-08-26

110 commits to master branch, last one 2 years ago

chiselv carlosedp

17

97

mit

6

A RISC-V Core (RV32I) written in Chisel HDL

core fpga riscv chisel risc-v

Created 2021-09-27

318 commits to main branch, last one 5 months ago

chisel-operator FyraLabs

8

80

gpl-3.0

3

Kubernetes Operator for Chisel

k8s chisel inlets tunnel inletsdev tunneling inlets-pro kubernetes k8s-operator kubernetes-operator

Created 2023-05-11

272 commits to main branch, last one 6 days ago

Direct_Chisel Azumi67

25

77

mit

1

Establishing a Direct tunnel using chisel between Servers and Client - IPV4 | IPV6 - TCP | UDP - [5] Kharej [1] IRAN

tcp udp v2ray chisel tunnel openvpn wireguard

Created 2024-01-19

27 commits to main branch, last one 9 months ago

chisel-circt sifive

10

70

apache-2.0

18

Library to compile Chisel circuits using LLVM/MLIR (CIRCT)

mlir circt scala chisel

This repository has been archived (exclude archived)

Created 2021-01-14

50 commits to main branch, last one about a year ago

riscv32-cpu-chisel rhysd

4

60

mit

4

Learning how to make RISC-V 32bit CPU with Chisel

cpu chisel risc-v chisel3

Created 2021-08-22

67 commits to main branch, last one 3 years ago

lldb-symbolic luoqisheng

6

59

mit

2

lldb命令-symbolic

lldb chisel custom-commend

Created 2018-12-15

7 commits to master branch, last one 3 years ago

Chisel-FFT-generator IA-C-Lab-Fudan

17

56

unknown

2

FFT generator using Chisel

fft chisel rtl-generator

Created 2020-04-30

20 commits to master branch, last one 3 years ago

saturn-vectors ucb-bar

4

53

bsd-3-clause

15

Chisel RISC-V Vector 1.0 Implementation

cpu rvv chisel risc-v vectors microarchitecture

Created 2023-08-23

904 commits to master branch, last one 2 days ago