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ucb-bar
chipyard ucb-bar
648
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bsd-3-clause
86
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
rtl soc boom riscv chisel hwacha risc-v rocket firesim chipyard peripherals rocket-chip superscalar accelerators out-of-order chip-generator
Created 2016-10-24
4,976 commits to main branch, last one 17 hours ago