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An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Created
2016-10-24
4,997 commits to main branch, last one 20 hours ago
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
Created
2019-06-04
1,571 commits to main branch, last one 5 months ago
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
Created
2017-12-20
1,123 commits to main branch, last one 8 months ago
Fletcher: A framework to integrate FPGA accelerators with Apache Arrow
Created
2018-02-09
707 commits to develop branch, last one about a year ago
CSV spreadsheets and other material for AI accelerator survey papers
Created
2021-05-04
14 commits to main branch, last one 10 months ago
HLS-based Graph Processing Framework on FPGAs
Created
2020-04-09
202 commits to master branch, last one 2 years ago
SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
Created
2019-04-01
461,633 commits to sycl/unified/master branch, last one about a month ago
Intel® Query Processing Library (Intel® QPL)
Created
2020-09-17
514 commits to develop branch, last one 9 days ago
Intel® Data Mover Library (Intel® DML)
Created
2021-06-30
103 commits to develop branch, last one 2 months ago
The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.
Created
2023-04-07
30 commits to main branch, last one 7 months ago
[TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
Created
2022-07-09
291 commits to main branch, last one about a year ago