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An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Created
2016-10-24
4,997 commits to main branch, last one 20 hours ago
Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
Created
2017-07-17
951 commits to master branch, last one 3 months ago