ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Date Created 2016-10-24 (8 years ago)

Commits 4,995 (last one 16 days ago)

Stargazers 1,691 (5 this week)

Watchers 88 (0 this week)

Forks 663

License bsd-3-clause

Ranking

RepositoryStats indexes 595,856 repositories, of these ucb-bar/chipyard is ranked #30,922 (95th percentile) for total stargazers, and #21,187 for total watchers. Github reports the primary language for this repository as Scala, for repositories using this language it is ranked #95/1,999.

ucb-bar/chipyard is also tagged with popular topics, for these it's ranked: risc-v (#21/268), riscv (#15/167)

Other Information

ucb-bar/chipyard has 31 open pull requests on Github, 1,134 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 186 open issues and 489 closed issues.

There have been 22 releases, the latest one was published on 2024-09-30 (2 months ago) with the name Chipyard 1.13.0.

Homepage URL: https://chipyard.readthedocs.io/en/stable/

All Topics

rtl soc boom riscv chisel hwacha risc-v rocket firesim chipyard peripherals rocket-chip superscalar accelerators out-of-order chip-generator

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

2,387 commits on the default branch (main) since jan '22

Yearly Commits

Commits to the default branch (main) per year

Issue History

Languages

The primary language is Scala but there's also others...

updated: 2024-12-21 @ 01:57am, id: 71811858 / R_kgDOBEfDEg