ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Date Created 2016-10-24 (8 years ago)

Commits 4,976 (last one 18 hours ago)

Stargazers 1,635 (3 this week)

Watchers 86 (0 this week)

Forks 648

License bsd-3-clause

Ranking

RepositoryStats indexes 579,238 repositories, of these ucb-bar/chipyard is ranked #31,478 (95th percentile) for total stargazers, and #21,666 for total watchers. Github reports the primary language for this repository as Scala, for repositories using this language it is ranked #99/1,982.

ucb-bar/chipyard is also tagged with popular topics, for these it's ranked: risc-v (#22/261), riscv (#16/165)

Other Information

ucb-bar/chipyard has 31 open pull requests on Github, 1,126 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 184 open issues and 486 closed issues.

There have been 22 releases, the latest one was published on 2024-09-30 (about a month ago) with the name Chipyard 1.13.0.

Homepage URL: https://chipyard.readthedocs.io/en/stable/

All Topics

rtl soc boom riscv chisel hwacha risc-v rocket firesim chipyard peripherals rocket-chip superscalar accelerators out-of-order chip-generator

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Github watchers over time, collection started in '23

Recent Commit History

2,368 commits on the default branch (main) since jan '22

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Languages

The primary language is Scala but there's also others...

updated: 2024-11-06 @ 09:33pm, id: 71811858 / R_kgDOBEfDEg