ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Date Created 2016-10-24 (7 years ago)

Commits 4,649 (last one 17 hours ago)

Stargazers 1,485 (3 this week)

Watchers 83 (0 this week)

Forks 601

License bsd-3-clause

Ranking

RepositoryStats indexes 534,551 repositories, of these ucb-bar/chipyard is ranked #33,243 (94th percentile) for total stargazers, and #22,397 for total watchers. Github reports the primary language for this repository as Scala, for repositories using this language it is ranked #112/1,924.

ucb-bar/chipyard is also tagged with popular topics, for these it's ranked: risc-v (#19/225), riscv (#14/147)

Other Information

ucb-bar/chipyard has 20 open pull requests on Github, 1,020 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 161 open issues and 471 closed issues.

There have been 17 releases, the latest one was published on 2024-01-23 (5 months ago) with the name Chipyard 1.11.0 Release.

Homepage URL: https://chipyard.readthedocs.io/en/stable/

All Topics

rtl soc boom riscv chisel hwacha risc-v rocket firesim chipyard peripherals rocket-chip superscalar accelerators out-of-order chip-generator

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Recent Commit History

2,040 commits on the default branch (main) since jan '22

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Languages

The primary language is Scala but there's also others...

updated: 2024-06-28 @ 09:32pm, id: 71811858 / R_kgDOBEfDEg