ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Date Created 2016-10-24 (8 years ago)

Commits 5,017 (last one a day ago)

Stargazers 1,733 (3 this week)

Watchers 89 (0 this week)

Forks 678

License bsd-3-clause

Ranking

RepositoryStats indexes 610,149 repositories, of these ucb-bar/chipyard is ranked #30,654 (95th percentile) for total stargazers, and #20,928 for total watchers. Github reports the primary language for this repository as Scala, for repositories using this language it is ranked #94/2,013.

ucb-bar/chipyard is also tagged with popular topics, for these it's ranked: risc-v (#21/270), riscv (#15/173)

Other Information

ucb-bar/chipyard has 29 open pull requests on Github, 1,144 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 186 open issues and 490 closed issues.

There have been 22 releases, the latest one was published on 2024-09-30 (4 months ago) with the name Chipyard 1.13.0.

Homepage URL: https://chipyard.readthedocs.io/en/stable/

All Topics

rtl soc boom riscv chisel hwacha risc-v rocket firesim chipyard peripherals rocket-chip superscalar accelerators out-of-order chip-generator

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Recent Commit History

2,409 commits on the default branch (main) since jan '22

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Languages

The primary language is Scala but there's also others...

updated: 2025-02-03 @ 02:33am, id: 71811858 / R_kgDOBEfDEg