6 results found Sort:

ucb-bar
chipyard ucb-bar
696
1.8k
bsd-3-clause
91
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
rtl soc boom riscv chisel hwacha risc-v rocket firesim chipyard peripherals rocket-chip superscalar accelerators out-of-order chip-generator
Created 2016-10-24
5,518 commits to main branch, last one 17 hours ago
RRZE-HPC
OSACA RRZE-HPC
21
319
agpl-3.0
25
Open Source Architecture Code Analyzer
avx hpc sve x86 avx2 neon avx512 python aarch64 arm64v8 in-core latency assembly throughput out-of-order port-mapping critical-path performance-analysis performance-modeling loop-carried-dependency
Created 2017-03-02
1,081 commits to master branch, last one 15 days ago
mathis-s
SoomRV mathis-s
16
203
mit
3
A simple superscalar out-of-order RISC-V microprocessor
cpu ooo risc-v out-of-order systemverilog computer-architecture
Created 2022-09-10
495 commits to master branch, last one about a month ago
riscv-software-src
riscv-perf-model riscv-software-src
66
163
apache-2.0
28
Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
risc-v modeling out-of-order performance-analysis
Created 2022-08-15
130 commits to master branch, last one 20 days ago
NOP-Processor
NOP-Core NOP-Processor
5
78
mit
1
High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
loongarch processor spinalhdl loongarch32r out-of-order
Created 2023-08-17
7 commits to master branch, last one about a year ago
sifferman
labs-with-cva6 sifferman
26
57
bsd-3-clause
2
Advanced Architecture Labs with CVA6
cva6 risc-v caching education out-of-order systemverilog virtual-memory branch-prediction
Created 2022-12-21
93 commits to main branch, last one about a year ago