12 results found Sort:
- Filter by Primary Language:
- Scala (8)
- C (2)
- Assembly (1)
- HTML (1)
- +
A FPGA friendly 32 bit RISC-V CPU implementation
Created
2017-03-08
1,620 commits to master branch, last one about a month ago
CNN accelerator implemented with Spinal HDL
Created
2021-12-27
115 commits to dev branch, last one about a year ago
客制化机械键盘——从0开始全套资料
Created
2020-01-16
41 commits to master branch, last one about a year ago
[HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
Created
2023-10-28
16 commits to main branch, last one 8 months ago
A reimplementation of a tiny stack CPU
Created
2017-02-25
734 commits to master branch, last one 4 years ago
High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
Created
2023-08-17
7 commits to master branch, last one about a year ago
Clio, ASPLOS'22.
Created
2021-07-15
500 commits to master branch, last one 3 years ago
An High-Performance SLAM Hardware Accelerator Implementation for FPGA
Created
2024-07-07
67 commits to main branch, last one 4 months ago
SpinalHDL - Cryptography libraries
Created
2017-04-12
170 commits to master branch, last one 8 months ago
The SpinalHDL design of the Proteus core, an extensible RISC-V core.
Created
2022-12-30
444 commits to main branch, last one 26 days ago
Translated SpinalHDL-Doc(v1.7.2) into Chinese
Created
2022-09-30
72 commits to main branch, last one 2 years ago