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VexRiscv SpinalHDL

384

2.3k

mit

98

A FPGA friendly 32 bit RISC-V CPU implementation

cpu soc fpga vhdl riscv verilog softcore spinalhdl

Created 2017-03-08

1,589 commits to master branch, last one 2 months ago

SpinalHDL_CNN_Accelerator 19801201

32

121

gpl-3.0

5

CNN accelerator implemented with Spinal HDL

cnn fpga yolo xilinx spinalhdl object-detection

Created 2021-12-27

115 commits to dev branch, last one 6 months ago

Keyboard volatile-static

19

84

unknown

4

客制化机械键盘——从0开始全套资料

ble ps2 fpga nios usb-hid verilog embedded keyboard nrf52832 wireless spinalhdl stm32f103c8t6

Created 2020-01-16

41 commits to master branch, last one 9 months ago

J1Sc SteffenReith

7

77

bsd-3-clause

12

A reimplementation of a tiny stack CPU

cpu hdl fpga vhdl forth j1-cpu verilog spinalhdl

Created 2017-02-25

734 commits to master branch, last one 3 years ago

Clio WukLab

7

67

mit

4

Clio, ASPLOS'22.

fpga spinalhdl libibverbs disaggregation

Created 2021-07-15

500 commits to master branch, last one 2 years ago

NOP-Core NOP-Processor

5

55

mit

1

High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)

loongarch processor spinalhdl loongarch32r out-of-order

Created 2023-08-17

7 commits to master branch, last one 9 months ago

spatten-llm mit-han-lab

3

51

mit

8

[HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning

rtl attention spinalhdl llm-inference hardware-acceleration

Created 2023-10-28

10 commits to main branch, last one 28 days ago

SpinalHDL_Chinese_Doc thuCGRA

6

41

unknown

3

Translated SpinalHDL-Doc(v1.7.2) into Chinese

spinalhdl documentation chinese-translation

Created 2022-09-30

72 commits to main branch, last one about a year ago

proteus proteus-core

7

36

mit

2

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

cpu rtl fpga riscv risc-v verilog hardware research security spinalhdl

Created 2022-12-30

414 commits to main branch, last one 23 days ago