agra-uni-bremen / microrv32

SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype

agra-uni-bremen
agra-uni-bremen
Date Created 2021-05-17 (3 years ago)
Commits 32 (last one 5 months ago)
Stargazers 45 (0 this week)
Watchers 11 (0 this week)
Forks 6
License mit
Ranking

RepositoryStats indexes 633,559 repositories, of these agra-uni-bremen/microrv32 is ranked #519,436 (18th percentile) for total stargazers, and #186,327 for total watchers. Github reports the primary language for this repository as Scala, for repositories using this language it is ranked #1,858/2,038.

agra-uni-bremen/microrv32 is also tagged with popular topics, for these it's ranked: fpga (#454/515),  verilog (#267/309),  cpu (#272/298),  risc-v (#238/283),  riscv (#154/181)

Other Information

agra-uni-bremen/microrv32 has 1 open pull request on Github, 0 pull requests have been merged over the lifetime of the repository.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

17 commits on the default branch (master) since jan '22

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Yearly Commits

Commits to the default branch (master) per year

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Issue History

No issues have been posted

Languages

The primary language is Scala but there's also others...

ScalaScalaCCAssemblyAssemblyMakefileMakefilePythonPythonC++C++ShellShellVerilogVerilog

updated: 2025-03-18 @ 04:17am, id: 368182040 / R_kgDOFfIDGA