SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

SpinalHDL
SpinalHDL
Date Created 2017-03-08 (8 years ago)
Commits 1,620 (last one about a month ago)
Stargazers 2,708 (5 this week)
Watchers 103 (0 this week)
Forks 436
License mit
Ranking

RepositoryStats indexes 633,155 repositories, of these SpinalHDL/VexRiscv is ranked #19,699 (97th percentile) for total stargazers, and #17,308 for total watchers. Github reports the primary language for this repository as Assembly, for repositories using this language it is ranked #23/1,062.

SpinalHDL/VexRiscv is also tagged with popular topics, for these it's ranked: fpga (#8/515),  verilog (#6/308),  cpu (#23/298),  riscv (#9/181)

Other Information

SpinalHDL/VexRiscv has 5 open pull requests on Github, 86 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 108 open issues and 236 closed issues.

Star History

Github stargazers over time

3k3k2.5k2.5k2k2k1.5k1.5k1k1k500500002018201820192019202020202021202120222022202320232024202420252025

Watcher History

Github watchers over time, collection started in '23

1031031021021011011001009999989897979696959520232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Recent Commit History

275 commits on the default branch (master) since jan '22

300300250250200200150150100100505000Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
Open Issues
Closed Issues
3503503003002502502002001501501001005050002018201820192019202020202021202120222022202320232024202420252025

Languages

The primary language is Assembly but there's also others...

AssemblyAssemblyScalaScalaC++C++CCTclTclMakefileMakefileVerilogVerilogPythonPythonCoqCoqShellShellOtherOther

updated: 2025-03-31 @ 03:11am, id: 84366787 / R_kgDOBQdVww