SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

Date Created 2017-03-08 (7 years ago)

Commits 1,614 (last one 18 days ago)

Stargazers 2,523 (2 this week)

Watchers 102 (0 this week)

Forks 420

License mit

Ranking

RepositoryStats indexes 589,134 repositories, of these SpinalHDL/VexRiscv is ranked #20,240 (97th percentile) for total stargazers, and #17,539 for total watchers. Github reports the primary language for this repository as Assembly, for repositories using this language it is ranked #24/973.

SpinalHDL/VexRiscv is also tagged with popular topics, for these it's ranked: fpga (#8/482), cpu (#25/285), verilog (#7/284), riscv (#9/167)

Other Information

SpinalHDL/VexRiscv has 5 open pull requests on Github, 84 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 100 open issues and 234 closed issues.

All Topics

cpu soc fpga vhdl riscv verilog softcore spinalhdl

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

269 commits on the default branch (master) since jan '22

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Languages

The primary language is Assembly but there's also others...

updated: 2024-12-01 @ 04:18am, id: 84366787 / R_kgDOBQdVww