SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

Date Created 2017-03-08 (7 years ago)

Commits 1,589 (last one 2 months ago)

Stargazers 2,292 (5 this week)

Watchers 98 (0 this week)

Forks 384

License mit

Ranking

RepositoryStats indexes 523,840 repositories, of these SpinalHDL/VexRiscv is ranked #20,876 (96th percentile) for total stargazers, and #18,256 for total watchers. Github reports the primary language for this repository as Assembly, for repositories using this language it is ranked #24/855.

SpinalHDL/VexRiscv is also tagged with popular topics, for these it's ranked: fpga (#8/425), verilog (#6/251), riscv (#8/146)

Other Information

SpinalHDL/VexRiscv has 5 open pull requests on Github, 75 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 101 open issues and 214 closed issues.

All Topics

cpu soc fpga vhdl riscv verilog softcore spinalhdl

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

244 commits on the default branch (master) since jan '22

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Languages

The primary language is Assembly but there's also others...

updated: 2024-05-30 @ 05:52pm, id: 84366787 / R_kgDOBQdVww