SteffenReith / J1Sc

A reimplementation of a tiny stack CPU

Date Created 2017-02-25 (7 years ago)

Commits 734 (last one 4 years ago)

Stargazers 80 (0 this week)

Watchers 12 (0 this week)

Forks 7

License bsd-3-clause

Ranking

RepositoryStats indexes 589,134 repositories, of these SteffenReith/J1Sc is ranked #339,400 (42nd percentile) for total stargazers, and #178,097 for total watchers. Github reports the primary language for this repository as Scala, for repositories using this language it is ranked #1,299/1,989.

SteffenReith/J1Sc is also tagged with popular topics, for these it's ranked: fpga (#300/482), cpu (#200/285), verilog (#185/284)

Other Information

SteffenReith/J1Sc has Github issues enabled, there are 4 open issues and 1 closed issue.

All Topics

cpu hdl fpga vhdl forth j1-cpu verilog spinalhdl

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0 commits on the default branch (master) since jan '22

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The primary language is Scala but there's also others...

updated: 2024-11-05 @ 02:34pm, id: 83146735 / R_kgDOBPS37w