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1.5k

bsd-3-clause

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

rtl soc boom riscv chisel hwacha risc-v rocket firesim chipyard peripherals rocket-chip superscalar accelerators out-of-order chip-generator

Created 2016-10-24

4,649 commits to main branch, last one 17 hours ago

139

799

apache-2.0

32-bit Superscalar RISC-V CPU

cpu asic fpga linux rv32i risc-v rv32im xilinx artix-7 verilog coremark in-order verilator riscv-linux superscalar branch-prediction pipelined-processors

Created 2020-02-10

37 commits to master branch, last one 2 years ago