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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Created
2018-04-12
1,318 commits to master branch, last one 29 days ago
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
Created
2019-06-04
1,616 commits to main branch, last one about a month ago
A Chisel RTL generator for network-on-chip interconnects
Created
2021-10-04
411 commits to master branch, last one 3 months ago
Network on Chip Implementation written in SytemVerilog
Created
2017-12-12
193 commits to master branch, last one 2 years ago
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
Created
2020-03-14
181 commits to master branch, last one 3 months ago