pulp-platform / axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Date Created 2018-04-12 (6 years ago)

Commits 1,248 (last one 23 days ago)

Stargazers 951 (3 this week)

Watchers 38 (0 this week)

Forks 242

License other

Ranking

RepositoryStats indexes 523,840 repositories, of these pulp-platform/axi is ranked #49,899 (90th percentile) for total stargazers, and #55,668 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #6/152.

pulp-platform/axi is also tagged with popular topics, for these it's ranked: fpga (#36/425), hardware (#52/386)

Other Information

pulp-platform/axi has 15 open pull requests on Github, 183 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 40 open issues and 77 closed issues.

There have been 56 releases, the latest one was published on 2024-05-08 (23 days ago)

All Topics

ip axi rtl asic axi4 fpga hardware axi4-lite systemverilog network-on-chip

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

282 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-05-31 @ 06:14pm, id: 129229399 / R_kgDOB7PiVw