pulp-platform / axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Date Created 2018-04-12 (6 years ago)

Commits 1,323 (last one 2 days ago)

Stargazers 1,240 (7 this week)

Watchers 40 (0 this week)

Forks 278

License other

Ranking

RepositoryStats indexes 630,459 repositories, of these pulp-platform/axi is ranked #43,695 (93rd percentile) for total stargazers, and #53,114 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #4/196.

pulp-platform/axi is also tagged with popular topics, for these it's ranked: fpga (#33/515), hardware (#53/476)

Other Information

pulp-platform/axi has 9 open pull requests on Github, 206 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 45 open issues and 80 closed issues.

There have been 59 releases, the latest one was published on 2024-12-04 (3 months ago) with the name v0.39.6.

All Topics

ip axi rtl asic axi4 fpga hardware axi4-lite systemverilog network-on-chip

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

357 commits on the default branch (master) since jan '22

Yearly Commits

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Issue History

Languages

The primary language is SystemVerilog but there's also others...

updated: 2025-03-22 @ 01:50pm, id: 129229399 / R_kgDOB7PiVw