pulp-platform / axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Date Created 2018-04-12 (6 years ago)

Commits 1,296 (last one 27 days ago)

Stargazers 1,113 (7 this week)

Watchers 39 (0 this week)

Forks 268

License other

Ranking

RepositoryStats indexes 584,353 repositories, of these pulp-platform/axi is ranked #46,081 (92nd percentile) for total stargazers, and #54,984 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #5/173.

pulp-platform/axi is also tagged with popular topics, for these it's ranked: fpga (#33/478), hardware (#51/446)

Other Information

pulp-platform/axi has 17 open pull requests on Github, 192 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 44 open issues and 78 closed issues.

There have been 58 releases, the latest one was published on 2024-10-24 (27 days ago) with the name v0.39.5.

All Topics

ip axi rtl asic axi4 fpga hardware axi4-lite systemverilog network-on-chip

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

330 commits on the default branch (master) since jan '22

Yearly Commits

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Issue History

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-11-20 @ 06:16pm, id: 129229399 / R_kgDOB7PiVw