3 results found Sort:

275
1.2k
other
40
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Created 2018-04-12
1,318 commits to master branch, last one 29 days ago
19
133
other
11
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
Created 2018-03-17
659 commits to main branch, last one 2 months ago
An AXI4 crossbar implementation in SystemVerilog
Created 2021-09-23
58 commits to main branch, last one a day ago