3 results found Sort:

pulp-platform
axi pulp-platform
242
951
other
38
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
ip axi rtl asic axi4 fpga hardware axi4-lite systemverilog network-on-chip
Created 2018-04-12
1,248 commits to master branch, last one 23 days ago
OSVVM
AXI4 OSVVM
15
104
other
11
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
tlm vip axi4 vhdl osvvm axi4-lite testbench simulation axi4-stream verification simulation-modeling verification-component
Created 2018-03-17
614 commits to main branch, last one 10 days ago
dpretet
axi-crossbar dpretet
23
91
mit
2
An AXI4 crossbar implementation in SystemVerilog
arm soc amba asic axi4 fpga riscv riscv32 riscv64 verilog crossbar fpga-soc monodraw axi4-full axi4-lite processor asic-design interconnect axi4-protocol
Created 2021-09-23
50 commits to main branch, last one 12 days ago