3 results found Sort:

pulp-platform
axi pulp-platform
267
1.1k
other
39
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
ip axi rtl asic axi4 fpga hardware axi4-lite systemverilog network-on-chip
Created 2018-04-12
1,296 commits to master branch, last one 29 days ago
OSVVM
AXI4 OSVVM
18
129
other
11
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
tlm vip axi4 vhdl osvvm axi4-lite testbench simulation axi4-stream verification simulation-modeling verification-component
Created 2018-03-17
654 commits to main branch, last one about a month ago
dpretet
axi-crossbar dpretet
26
123
mit
3
An AXI4 crossbar implementation in SystemVerilog
arm soc amba asic axi4 fpga riscv riscv32 riscv64 verilog crossbar fpga-soc monodraw axi4-full axi4-lite processor asic-design interconnect axi4-protocol
Created 2021-09-23
50 commits to main branch, last one 6 months ago