dpretet / axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

Date Created 2021-09-23 (2 years ago)

Commits 50 (last one 12 days ago)

Stargazers 91 (0 this week)

Watchers 2 (0 this week)

Forks 23

License mit

Ranking

RepositoryStats indexes 523,840 repositories, of these dpretet/axi-crossbar is ranked #285,719 (45th percentile) for total stargazers, and #442,567 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #66/152.

dpretet/axi-crossbar is also tagged with popular topics, for these it's ranked: fpga (#239/425), arm (#285/405), verilog (#145/251), riscv (#89/146)

Other Information

dpretet/axi-crossbar has Github issues enabled, there are 7 open issues and 7 closed issues.

There have been 5 releases, the latest one was published on 2024-05-15 (16 days ago) with the name v1.0.1 - CDC Fix Release.

All Topics

arm soc amba asic axi4 fpga riscv riscv32 riscv64 verilog crossbar fpga-soc monodraw axi4-full axi4-lite processor asic-design interconnect axi4-protocol

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

15 commits on the default branch (main) since jan '22

Yearly Commits

Commits to the default branch (main) per year

Issue History

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-05-30 @ 05:28am, id: 409702283 / R_kgDOGGuPiw