dpretet / axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

Date Created 2021-09-23 (3 years ago)

Commits 50 (last one 6 months ago)

Stargazers 123 (0 this week)

Watchers 3 (0 this week)

Forks 26

License mit

Ranking

RepositoryStats indexes 585,332 repositories, of these dpretet/axi-crossbar is ranked #252,474 (57th percentile) for total stargazers, and #422,835 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #62/173.

dpretet/axi-crossbar is also tagged with popular topics, for these it's ranked: fpga (#213/478), arm (#254/438), verilog (#134/282), riscv (#90/166)

Other Information

dpretet/axi-crossbar has Github issues enabled, there are 12 open issues and 7 closed issues.

There have been 5 releases, the latest one was published on 2024-05-15 (6 months ago) with the name v1.0.1 - CDC Fix Release.

All Topics

arm soc amba asic axi4 fpga riscv riscv32 riscv64 verilog crossbar fpga-soc monodraw axi4-full axi4-lite processor asic-design interconnect axi4-protocol

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Recent Commit History

15 commits on the default branch (main) since jan '22

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Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-11-22 @ 06:52am, id: 409702283 / R_kgDOGGuPiw