dpretet / axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

Date Created 2021-09-23 (3 years ago)

Commits 57 (last one about a month ago)

Stargazers 125 (0 this week)

Watchers 3 (0 this week)

Forks 26

License mit

Ranking

RepositoryStats indexes 597,394 repositories, of these dpretet/axi-crossbar is ranked #253,145 (58th percentile) for total stargazers, and #428,216 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #62/178.

dpretet/axi-crossbar is also tagged with popular topics, for these it's ranked: fpga (#213/489), arm (#257/446), verilog (#135/291), riscv (#90/167)

Other Information

dpretet/axi-crossbar has Github issues enabled, there are 11 open issues and 8 closed issues.

There have been 6 releases, the latest one was published on 2024-11-26 (29 days ago) with the name v1.0.2 - Fix AXI protocol violation & remove read data interleaving.

All Topics

arm soc amba asic axi4 fpga riscv riscv32 riscv64 verilog crossbar fpga-soc monodraw axi4-full axi4-lite processor asic-design interconnect axi4-protocol

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Recent Commit History

22 commits on the default branch (main) since jan '22

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Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-12-12 @ 11:40pm, id: 409702283 / R_kgDOGGuPiw