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dpretet
axi-crossbar dpretet
24
100
mit
2
An AXI4 crossbar implementation in SystemVerilog
arm soc amba asic axi4 fpga riscv riscv32 riscv64 verilog crossbar fpga-soc monodraw axi4-full axi4-lite processor asic-design interconnect axi4-protocol
Created 2021-09-23
50 commits to main branch, last one about a month ago