OSVVM / AXI4

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

Date Created 2018-03-17 (6 years ago)

Commits 654 (last one 26 days ago)

Stargazers 129 (0 this week)

Watchers 11 (0 this week)

Forks 18

License other

Ranking

RepositoryStats indexes 579,555 repositories, of these OSVVM/AXI4 is ranked #242,426 (58th percentile) for total stargazers, and #190,647 for total watchers. Github reports the primary language for this repository as VHDL, for repositories using this language it is ranked #56/176.

OSVVM/AXI4 is also tagged with popular topics, for these it's ranked: simulation (#433/996)

Other Information

OSVVM/AXI4 has Github issues enabled, there are 6 open issues and 12 closed issues.

All Topics

tlm vip axi4 vhdl osvvm axi4-lite testbench simulation axi4-stream verification simulation-modeling verification-component

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

240 commits on the default branch (main) since jan '22

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Commits to the default branch (main) per year

Issue History

Languages

The only known language in this repository is VHDL

updated: 2024-11-07 @ 09:22am, id: 125653139 / R_kgDOB31Qkw