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Network on Chip Simulator
Created
2015-03-23
679 commits to master branch, last one 11 months ago
A Chisel RTL generator for network-on-chip interconnects
Created
2021-10-04
411 commits to master branch, last one about a month ago
Network on Chip Implementation written in SytemVerilog
Created
2017-12-12
193 commits to master branch, last one 2 years ago
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
Created
2020-03-14
181 commits to master branch, last one about a month ago
Official read only mirror for
Created
2017-10-21
39,529 commits to master branch, last one a day ago
OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
Created
2015-12-25
1,270 commits to master branch, last one 3 years ago
A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
Created
2024-06-06
92 commits to master branch, last one 3 months ago