16 results found Sort:

cocotb
cocotb cocotb
512
1.8k
bsd-3-clause
107
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
uvm test vhdl python verilog verification
Created 2013-06-12
4,277 commits to master branch, last one 2 days ago
maximecb
uvm maximecb
19
538
apache-2.0
20
Fun, portable, minimalistic virtual machine.
uvm rust bytecode compiler emulator emulation sandboxing interpreter jit-compiler permacomputing virtual-machine containerization bytecode-interpreter
Created 2022-06-11
999 commits to main branch, last one 2 months ago
openhwgroup
core-v-verif openhwgroup
222
447
other
48
Functional verification project for the CORE-V family of RISC-V cores.
uvm risc-v verification systemverilog
Created 2019-11-29
4,467 commits to master branch, last one a day ago
chipsalliance
Surelog chipsalliance
69
369
apache-2.0
27
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
uvm vpi antlr linter parser verilog vpi-api parser-ast python-api elaboration preprocessor vpi-standard systemverilog antlr4-grammar
Created 2019-10-30
6,618 commits to master branch, last one 7 days ago
taichi-ishitani
tvip-axi taichi-ishitani
105
363
apache-2.0
16
AMBA AXI VIP
axi uvm vip amba axi4 amba-axi systemverilog
Created 2018-09-22
113 commits to master branch, last one 4 months ago
rggen
rggen rggen
43
331
mit
14
Code generation tool for control and status registers
apb axi csr eda ral rtl soc uvm amba asic fpga vhdl verilog wishbone-bus systemverilog uvm-ral-model wiki-documents uvm-register-model register-descriptions
Created 2019-04-10
379 commits to master branch, last one 6 days ago
troyguo
awesome-dv troyguo
66
266
unknown
11
Awesome ASIC design verification
uvm asic verification asic-verification formal-verification
Created 2020-03-02
19 commits to master branch, last one 2 years ago
Nic30
hwt Nic30
27
202
mit
18
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
hcl hls rtl uvm fpga vhdl codegen systemc verilog compiler simulator codegenerator systemverilog
Created 2015-05-19
3,348 commits to master branch, last one 16 hours ago
Juniper
open-register-design-tool Juniper
69
195
apache-2.0
44
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
eda uvm asic fpga jspec registers systemrdl systemverilog systemrdl-compiler register-descriptions
Created 2016-06-14
460 commits to master branch, last one about a month ago
taichi-ishitani
tnoc taichi-ishitani
44
158
apache-2.0
13
Network on Chip Implementation written in SytemVerilog
axi noc uvm amba axi4 amba-axi systemverilog network-on-chip
Created 2017-12-12
193 commits to master branch, last one 2 years ago
kumarrishav14
AXI kumarrishav14
34
108
mit
3
VIP for AXI Protocol
sv uvm amba-axi asic-verification design-verification
Created 2020-12-29
41 commits to main branch, last one 3 years ago
SystemRDL
PeakRDL SystemRDL
24
105
gpl-3.0
13
Control and status register code generator toolchain
apb axi csr eda uvm amba asic fpga verilog registers systemverilog command-line-tool systemrdl-compiler uvm-register-model register-descriptions hardware-description-language
Created 2020-04-05
67 commits to main branch, last one about a year ago
Siddhi-95
AHB-to-APB-Bridge-Verification Siddhi-95
17
71
unknown
1
Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
uvm verilog systemverilog
Created 2022-03-01
62 commits to main branch, last one about a year ago
dadongshangu
async_FIFO dadongshangu
15
54
mit
2
This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
uvm fifo async-fifo verilog-tb asynchronous verification-code
Created 2020-09-05
46 commits to master branch, last one about a year ago
SystemRDL
PeakRDL-uvm SystemRDL
27
51
gpl-3.0
10
Generate UVM register model from compiled SystemRDL input
eda uvm asic fpga registers uvm-ral-model uvm-register-model
Created 2019-08-23
47 commits to main branch, last one about a year ago
Shehab-Naga
ddr5_phy Shehab-Naga
22
42
mit
2
DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
gp uvm systemverilog
Created 2022-06-30
5 commits to main branch, last one 8 months ago