16 results found Sort:

cocotb
cocotb cocotb
481
1.6k
bsd-3-clause
106
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
uvm test vhdl python verilog verification
Created 2013-06-12
4,036 commits to master branch, last one a day ago
maximecb
uvm maximecb
20
505
apache-2.0
19
Fun, portable, minimalistic virtual machine.
uvm rust bytecode compiler emulator emulation sandboxing interpreter jit-compiler permacomputing virtual-machine containerization bytecode-interpreter
Created 2022-06-11
919 commits to main branch, last one about a month ago
openhwgroup
core-v-verif openhwgroup
203
391
other
48
Functional verification project for the CORE-V family of RISC-V cores.
uvm risc-v verification systemverilog
Created 2019-11-29
4,342 commits to master branch, last one 2 days ago
chipsalliance
Surelog chipsalliance
67
335
apache-2.0
26
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
uvm vpi antlr linter parser verilog vpi-api parser-ast python-api elaboration preprocessor vpi-standard systemverilog antlr4-grammar
Created 2019-10-30
6,502 commits to master branch, last one 17 days ago
taichi-ishitani
tvip-axi taichi-ishitani
98
322
apache-2.0
15
AMBA AXI VIP
axi uvm vip amba axi4 amba-axi systemverilog
Created 2018-09-22
110 commits to master branch, last one 16 days ago
rggen
rggen rggen
42
290
mit
14
Code generation tool for control and status registers
apb axi csr eda ral rtl soc uvm amba asic fpga vhdl verilog wishbone-bus systemverilog uvm-ral-model wiki-documents uvm-register-model register-descriptions
Created 2019-04-10
375 commits to master branch, last one 16 days ago
troyguo
awesome-dv troyguo
58
223
unknown
10
Awesome ASIC design verification
uvm asic verification asic-verification formal-verification
Created 2020-03-02
19 commits to master branch, last one 2 years ago
Nic30
hwt Nic30
26
194
mit
19
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
hcl hls rtl uvm fpga vhdl codegen systemc verilog compiler simulator codegenerator systemverilog
Created 2015-05-19
3,302 commits to master branch, last one 17 days ago
Juniper
open-register-design-tool Juniper
66
182
apache-2.0
43
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
eda uvm asic fpga jspec registers systemrdl systemverilog systemrdl-compiler register-descriptions
Created 2016-06-14
453 commits to master branch, last one 10 months ago
taichi-ishitani
tnoc taichi-ishitani
42
140
apache-2.0
13
Network on Chip Implementation written in SytemVerilog
axi noc uvm amba axi4 amba-axi systemverilog network-on-chip
Created 2017-12-12
193 commits to master branch, last one about a year ago
kumarrishav14
AXI kumarrishav14
27
86
mit
3
VIP for AXI Protocol
sv uvm amba-axi asic-verification design-verification
Created 2020-12-29
41 commits to main branch, last one 3 years ago
SystemRDL
PeakRDL SystemRDL
16
74
gpl-3.0
12
Control and status register code generator toolchain
apb axi csr eda uvm amba asic fpga verilog registers systemverilog command-line-tool systemrdl-compiler uvm-register-model register-descriptions hardware-description-language
Created 2020-04-05
67 commits to main branch, last one 6 months ago
Siddhi-95
AHB-to-APB-Bridge-Verification Siddhi-95
11
53
unknown
1
Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
uvm verilog systemverilog
Created 2022-03-01
62 commits to main branch, last one 11 months ago
dadongshangu
async_FIFO dadongshangu
15
48
mit
2
This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
uvm fifo async-fifo verilog-tb asynchronous verification-code
Created 2020-09-05
46 commits to master branch, last one 7 months ago
SystemRDL
PeakRDL-uvm SystemRDL
25
45
gpl-3.0
9
Generate UVM register model from compiled SystemRDL input
eda uvm asic fpga registers uvm-ral-model uvm-register-model
Created 2019-08-23
47 commits to main branch, last one 6 months ago
Shehab-Naga
ddr5_phy Shehab-Naga
16
37
mit
2
DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
gp uvm systemverilog
Created 2022-06-30
5 commits to main branch, last one 2 months ago