18 results found Sort:

533
1.9k
bsd-3-clause
107
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Created 2013-06-12
4,357 commits to master branch, last one 2 days ago
19
546
apache-2.0
20
Fun, portable, minimalistic virtual machine.
Created 2022-06-11
999 commits to main branch, last one 4 months ago
Functional verification project for the CORE-V family of RISC-V cores.
Created 2019-11-29
4,491 commits to master branch, last one 12 hours ago
68
381
apache-2.0
27
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Created 2019-10-30
6,622 commits to master branch, last one about a month ago
107
371
apache-2.0
16
AMBA AXI VIP
Created 2018-09-22
113 commits to master branch, last one 7 months ago
44
356
mit
15
Code generation tool for control and status registers
Created 2019-04-10
387 commits to master branch, last one 7 days ago
67
277
unknown
12
Awesome ASIC design verification
Created 2020-03-02
19 commits to master branch, last one 2 years ago
27
206
mit
18
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Created 2015-05-19
3,349 commits to master branch, last one 2 months ago
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Created 2016-06-14
460 commits to master branch, last one 3 months ago
45
165
apache-2.0
14
Network on Chip Implementation written in SytemVerilog
Created 2017-12-12
193 commits to master branch, last one 2 years ago
VIP for AXI Protocol
Created 2020-12-29
41 commits to main branch, last one 4 years ago
25
111
gpl-3.0
12
Control and status register code generator toolchain
Created 2020-04-05
77 commits to main branch, last one about a month ago
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
Created 2018-01-17
4 commits to master branch, last one about a month ago
Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
Created 2022-03-01
62 commits to main branch, last one about a year ago
This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
Created 2020-09-05
46 commits to master branch, last one about a year ago
29
51
gpl-3.0
11
Generate UVM register model from compiled SystemRDL input
Created 2019-08-23
47 commits to main branch, last one about a year ago
DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
Created 2022-06-30
5 commits to main branch, last one 10 months ago
Bitmap Processing Library & AXI-Stream Video Image VIP
Created 2022-04-11
2 commits to main branch, last one 2 years ago