Shehab-Naga / ddr5_phy

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

Shehab-Naga
Shehab-Naga
Date Created 2022-06-30 (about a year ago)
Commits 5 (last one 2 months ago)
Stargazers 37 (0 this week)
Watchers 2 (0 this week)
Forks 16
License mit
Ranking

RepositoryStats indexes 523,840 repositories, of these Shehab-Naga/ddr5_phy is ranked #481,096 (8th percentile) for total stargazers, and #442,567 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #135/152.

Other Information

Shehab-Naga/ddr5_phy has Github issues enabled, there is 1 open issue and 0 closed issues.

There have been 1 release, the latest one was published on 2022-06-30 (about a year ago) with the name DDR5 PHY Verification IP.

All Topics
gp uvm systemverilog

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

5 commits on the default branch (main) since jan '22

Yearly Commits

Commits to the default branch (main) per year

Issue History

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-05-30 @ 02:39pm, id: 509060808 / R_kgDOHlemyA