Shehab-Naga / ddr5_phy

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

Date Created 2022-06-30 (2 years ago)
Commits 5 (last one 11 months ago)
Stargazers 43 (0 this week)
Watchers 2 (0 this week)
Forks 26
License mit
Ranking

RepositoryStats indexes 618,350 repositories, of these Shehab-Naga/ddr5_phy is ranked #520,591 (16th percentile) for total stargazers, and #494,190 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #149/192.

Other Information

Shehab-Naga/ddr5_phy has Github issues enabled, there are 2 open issues and 0 closed issues.

There have been 1 release, the latest one was published on 2022-06-30 (2 years ago) with the name DDR5 PHY Verification IP.

All Topics

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

5 commits on the default branch (main) since jan '22

554.54.5443.53.5332.52.5221.51.5110.50.500Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (main) per year

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Issue History

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Languages

The primary language is SystemVerilog but there's also others...

SystemVerilogSystemVerilogShellShellCCForthForthEmacs LispEmacs Lisp

updated: 2025-02-20 @ 04:28pm, id: 509060808 / R_kgDOHlemyA