Shehab-Naga / ddr5_phy

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

Shehab-Naga
Shehab-Naga
Date Created 2022-06-30 (2 years ago)
Commits 5 (last one 8 months ago)
Stargazers 42 (0 this week)
Watchers 2 (0 this week)
Forks 22
License mit
Ranking

RepositoryStats indexes 589,134 repositories, of these Shehab-Naga/ddr5_phy is ranked #505,714 (14th percentile) for total stargazers, and #481,361 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #146/177.

Other Information

Shehab-Naga/ddr5_phy has Github issues enabled, there is 1 open issue and 0 closed issues.

There have been 1 release, the latest one was published on 2022-06-30 (2 years ago) with the name DDR5 PHY Verification IP.

All Topics
gp uvm systemverilog

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

5 commits on the default branch (main) since jan '22

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Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-11-13 @ 11:24am, id: 509060808 / R_kgDOHlemyA