Juniper / open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Date Created 2016-06-14 (8 years ago)
Commits 460 (last one 4 months ago)
Stargazers 196 (0 this week)
Watchers 44 (0 this week)
Forks 71
License apache-2.0
Ranking

RepositoryStats indexes 618,350 repositories, of these Juniper/open-register-design-tool is ranked #188,116 (70th percentile) for total stargazers, and #48,557 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #117/601.

Juniper/open-register-design-tool is also tagged with popular topics, for these it's ranked: fpga (#159/503),  eda (#59/145)

Other Information

Juniper/open-register-design-tool has Github issues enabled, there are 25 open issues and 62 closed issues.

There have been 15 releases, the latest one was published on 2023-07-28 (about a year ago) with the name 230719.01.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

20 commits on the default branch (master) since jan '22

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Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
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Closed Issues
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Languages

The primary language is Verilog but there's also others...

VerilogVerilogSystemVerilogSystemVerilogJavaJavaC++C++CCPythonPythonJavaScriptJavaScriptANTLRANTLRShellShell

updated: 2025-02-11 @ 05:41am, id: 61146698 / R_kgDOA6UGSg