Juniper / open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Date Created 2016-06-14 (8 years ago)

Commits 460 (last one 16 days ago)

Stargazers 195 (0 this week)

Watchers 44 (0 this week)

Forks 69

License apache-2.0

Ranking

RepositoryStats indexes 579,555 repositories, of these Juniper/open-register-design-tool is ranked #180,991 (69th percentile) for total stargazers, and #47,989 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #113/533.

Juniper/open-register-design-tool is also tagged with popular topics, for these it's ranked: fpga (#151/475), eda (#56/137)

Other Information

Juniper/open-register-design-tool has Github issues enabled, there are 24 open issues and 62 closed issues.

There have been 15 releases, the latest one was published on 2023-07-28 (about a year ago) with the name 230719.01.

All Topics

eda uvm asic fpga jspec registers systemrdl systemverilog systemrdl-compiler register-descriptions

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Recent Commit History

20 commits on the default branch (master) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2024-10-26 @ 04:49pm, id: 61146698 / R_kgDOA6UGSg