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Juniper
open-register-design-tool Juniper
70
194
apache-2.0
44
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
eda uvm asic fpga jspec registers systemrdl systemverilog systemrdl-compiler register-descriptions
Created 2016-06-14
460 commits to master branch, last one 2 months ago