5 results found Sort:

troyguo
awesome-dv troyguo
67
274
unknown
11
Awesome ASIC design verification
uvm asic verification asic-verification formal-verification
Created 2020-03-02
19 commits to master branch, last one 2 years ago
abdelazeem201
Systolic-array-implementation-in-RTL-for-TPU abdelazeem201
25
166
mit
2
IC implementation of Systolic Array for TPU
rtl asic fpga verilog asic-design asic-verification
Created 2021-01-07
67 commits to main branch, last one 2 months ago
kumarrishav14
AXI kumarrishav14
35
118
mit
3
VIP for AXI Protocol
sv uvm amba-axi asic-verification design-verification
Created 2020-12-29
41 commits to main branch, last one 3 years ago
wyvernSemi
vproc wyvernSemi
9
50
gpl-3.0
9
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
c cpp dpi pli vpi fpga vhdl dpi-c logic python verilog codesign processor vhpidirect cosimulation verification systemverilog logic-simulation asic-verification simulation-element
Created 2016-09-29
262 commits to master branch, last one 10 days ago
abdelazeem201
Design-and-ASIC-Implementation-of-32-Point-FFT-Processor abdelazeem201
1
39
mit
1
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has ...
fft rtl soc asic fpga vhdl verilog synthesis asic-design asic-verification
Created 2022-01-06
89 commits to main branch, last one about a year ago