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wyvernSemi
vproc wyvernSemi
9
51
gpl-3.0
9
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
c cpp dpi pli vpi fpga vhdl dpi-c logic python verilog codesign processor vhpidirect cosimulation verification systemverilog logic-simulation asic-verification simulation-element
Created 2016-09-29
264 commits to master branch, last one about a month ago