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PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
Created
2016-10-07
81 commits to master branch, last one 22 days ago
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
Created
2016-09-29
264 commits to master branch, last one about a month ago