wyvernSemi / pcievhost

PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities

Date Created 2016-10-07 (8 years ago)
Commits 79 (last one 13 days ago)
Stargazers 91 (0 this week)
Watchers 12 (0 this week)
Forks 21
License gpl-3.0
Ranking

RepositoryStats indexes 615,809 repositories, of these wyvernSemi/pcievhost is ranked #321,042 (48th percentile) for total stargazers, and #180,077 for total watchers. Github reports the primary language for this repository as C, for repositories using this language it is ranked #12,939/22,807.

wyvernSemi/pcievhost is also tagged with popular topics, for these it's ranked: c (#1,838/2819),  verilog (#172/299)

Other Information

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

59 commits on the default branch (master) since jan '22

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Issue History

Total Issues
Open Issues
Closed Issues
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Languages

The primary language is C but there's also others...

CCVerilogVerilogC++C++MakefileMakefileStataStata

updated: 2025-02-15 @ 05:24pm, id: 70256088 / R_kgDOBDAF2A