wyvernSemi / vproc

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments

Date Created 2016-09-29 (8 years ago)

Commits 262 (last one 10 days ago)

Stargazers 50 (1 this week)

Watchers 9 (0 this week)

Forks 9

License gpl-3.0

Ranking

RepositoryStats indexes 597,394 repositories, of these wyvernSemi/vproc is ranked #470,187 (21st percentile) for total stargazers, and #226,032 for total watchers. Github reports the primary language for this repository as VHDL, for repositories using this language it is ranked #143/186.

wyvernSemi/vproc is also tagged with popular topics, for these it's ranked: python (#18,767/22362), cpp (#2,872/3471), c (#2,403/2767), fpga (#405/489), verilog (#245/291)

Other Information

There have been 1 release, the latest one was published on 2024-12-05 (20 days ago) with the name Verilator Sim Control.

Homepage URL: http://www.anita-simulators.org.uk/wyvernsemi

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

224 commits on the default branch (master) since jan '22

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Languages

The primary language is VHDL but there's also others...

updated: 2024-12-23 @ 01:00am, id: 69550177 / R_kgDOBCVAYQ