abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.

Date Created 2022-01-06 (2 years ago)

Commits 89 (last one about a year ago)

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fft rtl soc asic fpga vhdl verilog synthesis asic-design asic-verification

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updated: 2024-12-21 @ 11:09am, id: 445140913 / R_kgDOGohPsQ