abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

IC implementation of Systolic Array for TPU

Date Created 2021-01-07 (3 years ago)

Commits 57 (last one 3 months ago)

Stargazers 118 (0 this week)

Watchers 2 (0 this week)

Forks 22

License mit

Ranking

RepositoryStats indexes 534,880 repositories, of these abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU is ranked #243,703 (54th percentile) for total stargazers, and #448,844 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #174/459.

abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU is also tagged with popular topics, for these it's ranked: fpga (#200/435), verilog (#127/257)

All Topics

rtl asic fpga verilog asic-design asic-verification

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17 commits on the default branch (main) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-06-19 @ 12:03pm, id: 327681879 / R_kgDOE4gHVw