abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

IC implementation of Systolic Array for TPU

Date Created 2021-01-07 (4 years ago)

Commits 67 (last one 5 months ago)

Stargazers 214 (8 this week)

Watchers 3 (0 this week)

Forks 26

License mit

Ranking

RepositoryStats indexes 632,768 repositories, of these abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU is ranked #179,307 (72nd percentile) for total stargazers, and #417,530 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #114/618.

abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU is also tagged with popular topics, for these it's ranked: fpga (#155/515), verilog (#98/308)

All Topics

rtl asic fpga verilog asic-design asic-verification

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Recent Commit History

27 commits on the default branch (main) since jan '22

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The primary language is Verilog but there's also others...

updated: 2025-03-27 @ 10:05pm, id: 327681879 / R_kgDOE4gHVw