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44

298

mit

14

Code generation tool for control and status registers

apb axi csr eda ral rtl soc uvm amba asic fpga vhdl verilog wishbone-bus systemverilog uvm-ral-model wiki-documents uvm-register-model register-descriptions

Created 2019-04-10

377 commits to master branch, last one 17 days ago

16

77

gpl-3.0

12

Control and status register code generator toolchain

apb axi csr eda uvm amba asic fpga verilog registers systemverilog command-line-tool systemrdl-compiler uvm-register-model register-descriptions hardware-description-language

Created 2020-04-05

67 commits to main branch, last one 7 months ago

25

45

gpl-3.0

9

Generate UVM register model from compiled SystemRDL input

eda uvm asic fpga registers uvm-ral-model uvm-register-model

Created 2019-08-23

47 commits to main branch, last one 7 months ago