SystemRDL / PeakRDL-uvm

Generate UVM register model from compiled SystemRDL input

Date Created 2019-08-23 (5 years ago)
Commits 47 (last one about a year ago)
Stargazers 51 (0 this week)
Watchers 11 (0 this week)
Forks 30
License gpl-3.0
Ranking

RepositoryStats indexes 618,350 repositories, of these SystemRDL/PeakRDL-uvm is ranked #476,526 (23rd percentile) for total stargazers, and #194,041 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #92,230/125,168.

SystemRDL/PeakRDL-uvm is also tagged with popular topics, for these it's ranked: fpga (#416/503),  eda (#124/145)

Other Information

SystemRDL/PeakRDL-uvm has 2 open pull requests on Github, 3 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 13 open issues and 15 closed issues.

There have been 9 releases, the latest one was published on 2023-03-12 (about a year ago) with the name 2.3.0.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

22 commits on the default branch (main) since jan '22

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Yearly Commits

Commits to the default branch (main) per year

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Issue History

Total Issues
Open Issues
Closed Issues
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Languages

The primary language is Python but there's also others...

PythonPythonSystemVerilogSystemVerilogShellShell

updated: 2025-02-02 @ 07:00pm, id: 203957612 / R_kgDODCglbA