dadongshangu / async_FIFO

This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

Date Created 2020-09-05 (3 years ago)

Commits 46 (last one 8 months ago)

Stargazers 50 (0 this week)

Watchers 2 (0 this week)

Forks 15

License mit

Ranking

RepositoryStats indexes 534,551 repositories, of these dadongshangu/async_FIFO is ranked #431,521 (19th percentile) for total stargazers, and #448,591 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #121/153.

Other Information

There have been 1 release, the latest one was published on 2020-09-17 (3 years ago) with the name First version of UVM testbench ready.

All Topics

uvm fifo async-fifo verilog-tb asynchronous verification-code

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2 commits on the default branch (master) since jan '22

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The primary language is SystemVerilog but there's also others...

updated: 2024-06-28 @ 05:10am, id: 292976057 / R_kgDOEXZ1uQ