openhwgroup / core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

Date Created 2019-11-29 (5 years ago)

Commits 4,477 (last one 10 days ago)

Stargazers 460 (1 this week)

Watchers 49 (0 this week)

Forks 228

License other

Ranking

RepositoryStats indexes 595,856 repositories, of these openhwgroup/core-v-verif is ranked #97,552 (84th percentile) for total stargazers, and #42,665 for total watchers. Github reports the primary language for this repository as Assembly, for repositories using this language it is ranked #114/991.

openhwgroup/core-v-verif is also tagged with popular topics, for these it's ranked: risc-v (#51/268)

Other Information

openhwgroup/core-v-verif has 14 open pull requests on Github, 1,792 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 123 open issues and 397 closed issues.

There have been 6 releases, the latest one was published on 2024-07-11 (5 months ago) with the name cv32e40p_v1.8.3.

Homepage URL: https://docs.openhwgroup.org/projects/core-v-verif/en/latest/index.html

All Topics

uvm risc-v verification systemverilog

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Github watchers over time, collection started in '23

Recent Commit History

1,274 commits on the default branch (master) since jan '22

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Languages

The primary language is Assembly but there's also others...

updated: 2024-12-20 @ 08:02am, id: 224885491 / R_kgDODWd68w