chipsalliance / Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Date Created 2019-10-30 (4 years ago)

Commits 6,527 (last one a day ago)

Stargazers 356 (1 this week)

Watchers 26 (0 this week)

Forks 68

License apache-2.0

Ranking

RepositoryStats indexes 565,279 repositories, of these chipsalliance/Surelog is ranked #114,270 (80th percentile) for total stargazers, and #84,064 for total watchers. Github reports the primary language for this repository as C++, for repositories using this language it is ranked #6,376/30,279.

chipsalliance/Surelog is also tagged with popular topics, for these it's ranked: parser (#296/1167), linter (#177/448), verilog (#63/272)

Other Information

chipsalliance/Surelog has Github issues enabled, there are 48 open issues and 867 closed issues.

All Topics

uvm vpi antlr linter parser verilog vpi-api parser-ast python-api elaboration preprocessor vpi-standard systemverilog antlr4-grammar

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

2,580 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is C++ but there's also others...

updated: 2024-09-28 @ 02:40pm, id: 218417034 / R_kgDODQTHig