chipsalliance / Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Date Created 2019-10-30 (5 years ago)
Commits 6,622 (last one 2 months ago)
Stargazers 381 (0 this week)
Watchers 26 (0 this week)
Forks 69
License apache-2.0
Ranking

RepositoryStats indexes 618,350 repositories, of these chipsalliance/Surelog is ranked #114,776 (81st percentile) for total stargazers, and #85,578 for total watchers. Github reports the primary language for this repository as C++, for repositories using this language it is ranked #6,381/33,023.

chipsalliance/Surelog is also tagged with popular topics, for these it's ranked: parser (#292/1238),  linter (#179/473),  verilog (#63/299)

Other Information

chipsalliance/Surelog has Github issues enabled, there are 52 open issues and 869 closed issues.

Star History

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

2,675 commits on the default branch (master) since jan '22

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Issue History

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Languages

The primary language is C++ but there's also others...

C++C++SystemVerilogSystemVerilogVerilogVerilogANTLRANTLRPythonPythonTclTclCMakeCMakeSlashSlashOtherOtherMakefileMakefileCap'n ProtoCap'n Proto

updated: 2025-02-11 @ 08:11pm, id: 218417034 / R_kgDODQTHig