chipsalliance / Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Date Created 2019-10-30 (5 years ago)

Commits 6,622 (last one 14 days ago)

Stargazers 374 (0 this week)

Watchers 27 (0 this week)

Forks 68

License apache-2.0

Ranking

RepositoryStats indexes 595,856 repositories, of these chipsalliance/Surelog is ranked #113,730 (81st percentile) for total stargazers, and #81,771 for total watchers. Github reports the primary language for this repository as C++, for repositories using this language it is ranked #6,334/31,836.

chipsalliance/Surelog is also tagged with popular topics, for these it's ranked: parser (#289/1208), linter (#180/465), verilog (#64/289)

Other Information

chipsalliance/Surelog has Github issues enabled, there are 51 open issues and 869 closed issues.

All Topics

uvm vpi antlr linter parser verilog vpi-api parser-ast python-api elaboration preprocessor vpi-standard systemverilog antlr4-grammar

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Recent Commit History

2,675 commits on the default branch (master) since jan '22

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Languages

The primary language is C++ but there's also others...

updated: 2024-12-21 @ 11:14am, id: 218417034 / R_kgDODQTHig