chipsalliance / Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Date Created 2019-10-30 (5 years ago)

Commits 6,644 (last one 7 days ago)

Stargazers 384 (1 this week)

Watchers 25 (0 this week)

Forks 71

License apache-2.0

Ranking

RepositoryStats indexes 632,894 repositories, of these chipsalliance/Surelog is ranked #115,736 (82nd percentile) for total stargazers, and #86,822 for total watchers. Github reports the primary language for this repository as C++, for repositories using this language it is ranked #6,444/33,733.

chipsalliance/Surelog is also tagged with popular topics, for these it's ranked: parser (#296/1251), linter (#180/481), verilog (#66/308)

Other Information

chipsalliance/Surelog has 3 open pull requests on Github, 3,029 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 52 open issues and 869 closed issues.

All Topics

uvm vpi antlr linter parser verilog vpi-api parser-ast python-api elaboration preprocessor vpi-standard systemverilog antlr4-grammar

Star History

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Github watchers over time, collection started in '23

Recent Commit History

2,697 commits on the default branch (master) since jan '22

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Languages

The primary language is C++ but there's also others...

updated: 2025-03-26 @ 11:57am, id: 218417034 / R_kgDODQTHig