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xls google

179

1.2k

apache-2.0

68

XLS: Accelerated HW Synthesis

hls verilog compiler pipeline open-source mid-level-synthesis high-level-synthesis

Created 2020-05-07

6,410 commits to main branch, last one 12 hours ago

PipelineC JulianKemmerer

49

602

gpl-3.0

24

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

c hls fpga vhdl python hardware pipelines fpga-programming fpga-acceleration fpga-accelerators hardware-description high-level-synthesis open-source-hardware hardware-description-language

Created 2018-05-03

1,721 commits to master branch, last one 4 days ago

calyx calyxir

52

499

mit

22

Intermediate Language (IL) for Hardware Accelerator Generators

compiler fpga-programming high-level-synthesis open-source-hardware intermediate-language

Created 2019-07-04

2,962 commits to main branch, last one 10 hours ago

dace spcl

129

498

bsd-3-clause

18

DaCe - Data Centric Parallel Programming

cuda fpga vivado-hls high-level-synthesis programming-language high-performance-computing

Created 2019-02-26

10,060 commits to main branch, last one 5 days ago

nngen NNgen

46

339

apache-2.0

21

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

onnx python compiler hardware pyverilog veriloggen verilog-hdl deep-learning neural-network high-level-synthesis

Created 2019-11-12

448 commits to develop branch, last one about a year ago

heterocl cornell-zhang

92

326

apache-2.0

17

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing

dsl fpga python compiler accelerators fpga-programming high-level-synthesis

Created 2017-12-20

1,123 commits to main branch, last one 7 months ago

gemm_hls spcl

53

307

bsd-3-clause

17

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

hls fpga vivado-hls high-level-synthesis

Created 2018-06-01

293 commits to master branch, last one 2 years ago

veriloggen PyHDI

58

305

apache-2.0

35

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

python compiler hardware pyverilog verilog-hdl high-level-synthesis hardware-construction-language

Created 2015-06-21

1,990 commits to develop branch, last one about a year ago

hlslib definelicht

56

303

bsd-3-clause

18

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

hpc fpga cmake vitis xilinx sdaccel intel-fpga vivado-hls intel-fpga-opencl high-level-synthesis

Created 2018-02-21

374 commits to master branch, last one 7 months ago

lenet5_hls changwoolee

92

299

mit

12

FPGA Accelerator for CNN using Vivado HLS

cnn hls sdx lenet sdsoc vivado accelerator high-level-synthesis

Created 2017-05-25

65 commits to master branch, last one 3 years ago

PandA-bambu ferrandi

48

244

gpl-3.0

16

PandA-bambu public repository

hls fpga hw-accelerators c-to-verilog-vhdl high-level-synthesis

Created 2017-08-18

6,231 commits to main branch, last one 7 months ago

poprc HackerFoo

10

243

gpl-3.0

19

A Compiler for the Popr Language

popr verilog compiler language functional linear-logic concatenative popr-compiler supercompiler dependent-types logic-programming non-deterministic partial-evaluators high-level-synthesis

Created 2012-10-07

1,802 commits to master branch, last one 3 years ago

hls_tutorial_examples spcl

46

192

bsd-3-clause

17

Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".

hls fpga opencl intel-fpga vivado-hls high-level-synthesis

Created 2018-02-24

107 commits to master branch, last one 3 years ago

allo cornell-zhang

28

146

apache-2.0

10

Allo: A Programming Model for Composable Accelerator Design

adl dsl asic fpga compiler hardware fpga-programming high-level-synthesis

Created 2023-07-21

242 commits to main branch, last one 2 days ago

dahlia cucapra

8

134

mit

11

Time-sensitive affine types for predictable hardware generation

dahlia fpga-programming high-level-synthesis open-source-hardware

Created 2018-05-22

1,801 commits to master branch, last one 7 months ago

CHARM arc-research-lab

20

124

mit

7

CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture

acap fpga versal versalacap deeplearning high-level-synthesis heterogeneous-computing design-space-exploration domain-specific-architecture electronic-design-automation

Created 2022-12-26

262 commits to main branch, last one 13 days ago

polyphony polyphony-dev

10

102

mit

17

Polyphony is Python based High-Level Synthesis compiler.

fpga python high-level-synthesis

Created 2015-11-30

470 commits to main branch, last one 5 years ago

vericert ymherklotz

5

88

gpl-3.0

12

A formally verified high-level synthesis tool based on CompCert and written in Coq.

coq high-level-synthesis

Created 2019-10-02

1,204 commits to master branch, last one 5 months ago

HiSparse cornell-zhang

11

80

bsd-3-clause

20

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

fpga-programming high-level-synthesis open-source-hardware sparse-linear-algebra

Created 2021-12-08

27 commits to master branch, last one about a month ago

GraphLily cornell-zhang

2

49

bsd-3-clause

14

A graph linear algebra overlay

fpga-programming graph-processing high-level-synthesis open-source-hardware

Created 2021-06-18

95 commits to master branch, last one 3 years ago

hcl-dialect cornell-zhang

17

40

other

16

HeteroCL-MLIR dialect for accelerator design

fpga compiler fpga-programming high-level-synthesis open-source-hardware intermediate-representation

Created 2021-11-18

1,145 commits to main branch, last one 2 months ago

apfp spcl

6

37

unknown

7

FPGA acceleration of arbitrary precision floating point computations.

gmp hls hpc fpga mpfr vitis bignum xilinx vivado-hls multiple-precision arbitrary-precision high-level-synthesis high-performance-computing

Created 2021-10-01

153 commits to main branch, last one 2 years ago