20 results found Sort:

google
xls google
166
1.1k
apache-2.0
62
XLS: Accelerated HW Synthesis
hls verilog compiler pipeline open-source mid-level-synthesis high-level-synthesis
Created 2020-05-07
5,179 commits to main branch, last one 11 hours ago
JulianKemmerer
PipelineC JulianKemmerer
45
557
gpl-3.0
24
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
c hls fpga vhdl python hardware pipelines fpga-programming fpga-acceleration fpga-accelerators hardware-description high-level-synthesis open-source-hardware hardware-description-language
Created 2018-05-03
1,584 commits to master branch, last one 12 days ago
spcl
dace spcl
116
469
bsd-3-clause
17
DaCe - Data Centric Parallel Programming
cuda fpga vivado-hls high-level-synthesis programming-language high-performance-computing
Created 2019-02-26
9,968 commits to master branch, last one a day ago
calyxir
calyx calyxir
45
453
mit
17
Intermediate Language (IL) for Hardware Accelerator Generators
compiler fpga-programming high-level-synthesis open-source-hardware intermediate-language
Created 2019-07-04
2,785 commits to main branch, last one 11 hours ago
NNgen
nngen NNgen
45
323
apache-2.0
20
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
onnx python compiler hardware pyverilog veriloggen verilog-hdl deep-learning neural-network high-level-synthesis
Created 2019-11-12
448 commits to develop branch, last one 7 months ago
cornell-zhang
heterocl cornell-zhang
95
316
apache-2.0
17
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
dsl fpga python compiler accelerators fpga-programming high-level-synthesis
Created 2017-12-20
1,123 commits to main branch, last one about a month ago
PyHDI
veriloggen PyHDI
57
298
apache-2.0
34
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
python compiler hardware pyverilog verilog-hdl high-level-synthesis hardware-construction-language
Created 2015-06-21
1,990 commits to develop branch, last one 9 months ago
definelicht
hlslib definelicht
51
293
bsd-3-clause
18
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
hpc fpga cmake vitis xilinx sdaccel intel-fpga vivado-hls intel-fpga-opencl high-level-synthesis
Created 2018-02-21
374 commits to master branch, last one about a month ago
changwoolee
lenet5_hls changwoolee
90
290
mit
12
FPGA Accelerator for CNN using Vivado HLS
cnn hls sdx lenet sdsoc vivado accelerator high-level-synthesis
Created 2017-05-25
65 commits to master branch, last one 2 years ago
spcl
gemm_hls spcl
50
290
bsd-3-clause
16
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
hls fpga vivado-hls high-level-synthesis
Created 2018-06-01
293 commits to master branch, last one 2 years ago
HackerFoo
poprc HackerFoo
10
234
gpl-3.0
20
A Compiler for the Popr Language
popr verilog compiler language functional linear-logic concatenative popr-compiler supercompiler dependent-types logic-programming non-deterministic partial-evaluators high-level-synthesis
Created 2012-10-07
1,802 commits to master branch, last one 3 years ago
ferrandi
PandA-bambu ferrandi
43
217
gpl-3.0
17
PandA-bambu public repository
hls fpga hw-accelerators c-to-verilog-vhdl high-level-synthesis
Created 2017-08-18
6,231 commits to main branch, last one 2 months ago
spcl
hls_tutorial_examples spcl
40
183
bsd-3-clause
18
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
hls fpga opencl intel-fpga vivado-hls high-level-synthesis
Created 2018-02-24
107 commits to master branch, last one 2 years ago
cucapra
dahlia cucapra
8
125
mit
10
Time-sensitive affine types for predictable hardware generation
dahlia fpga-programming high-level-synthesis open-source-hardware
Created 2018-05-22
1,801 commits to master branch, last one about a month ago
arc-research-lab
CHARM arc-research-lab
16
103
mit
6
CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture
acap fpga versal versalacap deeplearning high-level-synthesis heterogeneous-computing design-space-exploration domain-specific-architecture electronic-design-automation
Created 2022-12-26
250 commits to main branch, last one a day ago
polyphony-dev
polyphony polyphony-dev
9
99
mit
16
Polyphony is Python based High-Level Synthesis compiler.
fpga python high-level-synthesis
Created 2015-11-30
470 commits to main branch, last one 5 years ago
ymherklotz
vericert ymherklotz
5
85
gpl-3.0
12
A formally verified high-level synthesis tool based on CompCert and written in Coq.
coq high-level-synthesis
Created 2019-10-02
1,202 commits to master branch, last one 2 months ago
cornell-zhang
HiSparse cornell-zhang
9
75
bsd-3-clause
19
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
fpga-programming high-level-synthesis open-source-hardware sparse-linear-algebra
Created 2021-12-08
24 commits to master branch, last one 2 years ago
cornell-zhang
allo cornell-zhang
7
71
apache-2.0
11
Allo: A Programming Model for Composable Accelerator Design
adl dsl asic fpga compiler hardware fpga-programming high-level-synthesis
Created 2023-07-21
189 commits to main branch, last one 2 days ago
cornell-zhang
GraphLily cornell-zhang
2
47
bsd-3-clause
13
A graph linear algebra overlay
fpga-programming graph-processing high-level-synthesis open-source-hardware
Created 2021-06-18
95 commits to master branch, last one 2 years ago