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xls google

187

1.3k

apache-2.0

67

XLS: Accelerated HW Synthesis

hls verilog compiler pipeline open-source mid-level-synthesis high-level-synthesis

Created 2020-05-07

7,376 commits to main branch, last one 23 hours ago

PipelineC JulianKemmerer

50

640

gpl-3.0

26

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

c hls fpga vhdl python hardware pipelines fpga-programming fpga-acceleration fpga-accelerators hardware-description high-level-synthesis open-source-hardware hardware-description-language

Created 2018-05-03

1,819 commits to master branch, last one 23 hours ago

calyx calyxir

55

520

mit

21

Intermediate Language (IL) for Hardware Accelerator Generators

compiler fpga-programming high-level-synthesis open-source-hardware intermediate-language

Created 2019-07-04

3,018 commits to main branch, last one 2 days ago

dace spcl

133

516

bsd-3-clause

16

DaCe - Data Centric Parallel Programming

cuda fpga vivado-hls high-level-synthesis programming-language high-performance-computing

Created 2019-02-26

10,124 commits to main branch, last one 9 days ago

nngen NNgen

46

349

apache-2.0

20

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

onnx python compiler hardware pyverilog veriloggen verilog-hdl deep-learning neural-network high-level-synthesis

Created 2019-11-12

448 commits to develop branch, last one about a year ago

heterocl cornell-zhang

93

335

apache-2.0

16

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing

dsl fpga python compiler accelerators fpga-programming high-level-synthesis

Created 2017-12-20

1,123 commits to main branch, last one 11 months ago

gemm_hls spcl

57

332

bsd-3-clause

16

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

hls fpga vivado-hls high-level-synthesis

Created 2018-06-01

293 commits to master branch, last one 3 years ago

hlslib definelicht

59

319

bsd-3-clause

16

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

hpc fpga cmake vitis xilinx sdaccel intel-fpga vivado-hls intel-fpga-opencl high-level-synthesis

Created 2018-02-21

375 commits to master branch, last one 2 months ago

lenet5_hls changwoolee

92

315

mit

11

FPGA Accelerator for CNN using Vivado HLS

cnn hls sdx lenet sdsoc vivado accelerator high-level-synthesis

Created 2017-05-25

65 commits to master branch, last one 3 years ago

veriloggen PyHDI

58

313

apache-2.0

34

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

python compiler hardware pyverilog verilog-hdl high-level-synthesis hardware-construction-language

Created 2015-06-21

1,990 commits to develop branch, last one about a year ago

PandA-bambu ferrandi

50

260

gpl-3.0

13

PandA-bambu public repository

hls fpga hw-accelerators c-to-verilog-vhdl high-level-synthesis

Created 2017-08-18

6,299 commits to main branch, last one 3 days ago

poprc HackerFoo

11

246

gpl-3.0

18

A Compiler for the Popr Language

popr verilog compiler language functional linear-logic concatenative popr-compiler supercompiler dependent-types logic-programming non-deterministic partial-evaluators high-level-synthesis

Created 2012-10-07

1,802 commits to master branch, last one 4 years ago

allo cornell-zhang

37

217

apache-2.0

11

Allo: A Programming Model for Composable Accelerator Design

adl dsl asic fpga compiler hardware fpga-programming high-level-synthesis

Created 2023-07-21

291 commits to main branch, last one 3 days ago

hls_tutorial_examples spcl

46

199

bsd-3-clause

16

Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".

hls fpga opencl intel-fpga vivado-hls high-level-synthesis

Created 2018-02-24

107 commits to master branch, last one 3 years ago

dahlia cucapra

8

142

mit

9

Time-sensitive affine types for predictable hardware generation

dahlia fpga-programming high-level-synthesis open-source-hardware

Created 2018-05-22

1,801 commits to master branch, last one 11 months ago

CHARM arc-research-lab

22

132

mit

7

CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture

acap fpga versal versalacap deeplearning high-level-synthesis heterogeneous-computing design-space-exploration domain-specific-architecture electronic-design-automation

Created 2022-12-26

291 commits to main branch, last one 16 hours ago

polyphony polyphony-dev

10

103

mit

17

Polyphony is Python based High-Level Synthesis compiler.

fpga python high-level-synthesis

Created 2015-11-30

742 commits to main branch, last one 2 months ago

vericert ymherklotz

5

90

gpl-3.0

11

A formally verified high-level synthesis tool based on CompCert and written in Coq.

coq high-level-synthesis

Created 2019-10-02

1,204 commits to master branch, last one 9 months ago

HiSparse cornell-zhang

10

88

bsd-3-clause

19

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

fpga-programming high-level-synthesis open-source-hardware sparse-linear-algebra

Created 2021-12-08

27 commits to master branch, last one 6 months ago

GraphLily cornell-zhang

2

51

bsd-3-clause

13

A graph linear algebra overlay

fpga-programming graph-processing high-level-synthesis open-source-hardware

Created 2021-06-18

95 commits to master branch, last one 3 years ago

hcl-dialect cornell-zhang

15

40

other

15

HeteroCL-MLIR dialect for accelerator design

fpga compiler fpga-programming high-level-synthesis open-source-hardware intermediate-representation

Created 2021-11-18

1,145 commits to main branch, last one 6 months ago

apfp spcl

7

38

unknown

7

FPGA acceleration of arbitrary precision floating point computations.

gmp hls hpc fpga mpfr vitis bignum xilinx vivado-hls multiple-precision arbitrary-precision high-level-synthesis high-performance-computing

Created 2021-10-01

153 commits to main branch, last one 2 years ago

HLS-CNN FedericoSerafini

11

37

mit

3

High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.

cnn hdl hls rtl asic fpga vitis stream hardware parallel pipeline synthesis accelerator high-level-synthesis

Created 2022-06-17

181 commits to main branch, last one 8 months ago