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A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Created
2018-05-03
1,721 commits to master branch, last one 4 days ago
Vitis_Accel_Examples
Created
2019-10-13
1,885 commits to main branch, last one 6 days ago
Intermediate Language (IL) for Hardware Accelerator Generators
Created
2019-07-04
2,962 commits to main branch, last one 10 hours ago
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
Created
2017-12-20
1,123 commits to main branch, last one 7 months ago
A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.
Created
2020-03-18
28 commits to master branch, last one 3 years ago
Allo: A Programming Model for Composable Accelerator Design
Created
2023-07-21
242 commits to main branch, last one 2 days ago
Time-sensitive affine types for predictable hardware generation
Created
2018-05-22
1,801 commits to master branch, last one 7 months ago
assorted library of utility cores for amaranth HDL
Created
2021-06-26
166 commits to main branch, last one 2 months ago
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
Created
2021-12-08
27 commits to master branch, last one about a month ago
A new Hardware Design Language that keeps you in the driver's seat
Created
2022-08-08
462 commits to master branch, last one 15 hours ago
A graph linear algebra overlay
Created
2021-06-18
95 commits to master branch, last one 3 years ago
Intel Quartus Prime Synthesis Engine for Docker
Created
2022-07-25
12 commits to master branch, last one 9 months ago
HeteroCL-MLIR dialect for accelerator design
Created
2021-11-18
1,145 commits to main branch, last one 2 months ago