Xilinx / Vitis_Accel_Examples

Vitis_Accel_Examples

Xilinx
Xilinx
Date Created 2019-10-13 (4 years ago)
Commits 1,866 (last one 5 months ago)
Stargazers 483 (0 this week)
Watchers 23 (0 this week)
Forks 203
License mit
Ranking

RepositoryStats indexes 535,551 repositories, of these Xilinx/Vitis_Accel_Examples is ranked #88,219 (84th percentile) for total stargazers, and #94,230 for total watchers. Github reports the primary language for this repository as Makefile, for repositories using this language it is ranked #160/1,060.

Other Information

Xilinx/Vitis_Accel_Examples has 1 open pull request on Github, 4 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 7 open issues and 75 closed issues.

There have been 7 releases, the latest one was published on 2021-10-27 (2 years ago) with the name 2021.1_rel2.

Homepage URL: http://xilinx.github.io/Vitis_Accel_Examples/

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Recent Commit History

643 commits on the default branch (main) since jan '22

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The primary language is Makefile but there's also others...

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Xilinx/Vitis_Accel_Examples

updated: 2024-07-02 @ 07:35am, id: 214885806 / R_kgDODM7lrg