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Vitis In-Depth Tutorials
Created
2019-09-30
2,820 commits to 2024.1 branch, last one 5 days ago
Run Time for AIE and FPGA based platforms
Created
2018-05-30
7,717 commits to master branch, last one 13 hours ago
Vitis_Accel_Examples
Created
2019-10-13
1,866 commits to main branch, last one 5 months ago
Notes on the Red Pitaya Open Source Instrument
Created
2014-12-23
2,907 commits to master branch, last one about a month ago
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
Created
2018-02-21
374 commits to master branch, last one 2 months ago
100 Gbps TCP/IP stack for Vitis shells
Created
2020-11-11
15 commits to vitis_2022_1 branch, last one 2 months ago
VNx: Vitis Network Examples
Created
2020-07-28
286 commits to master branch, last one 2 months ago
Vitis Model Composer Examples and Tutorials
Created
2020-10-12
1,955 commits to 2024.1 branch, last one 18 days ago
Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
Created
2020-05-28
132 commits to master branch, last one about a year ago