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Vitis In-Depth Tutorials
Created
2019-09-30
2,943 commits to 2024.2 branch, last one 5 days ago
Run Time for AIE and FPGA based platforms
Created
2018-05-30
8,102 commits to master branch, last one 22 hours ago
Vitis_Accel_Examples
Created
2019-10-13
1,885 commits to main branch, last one 3 months ago
Notes on the Red Pitaya Open Source Instrument
Created
2014-12-23
2,931 commits to master branch, last one 12 days ago
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
Created
2018-02-21
375 commits to master branch, last one 29 days ago
100 Gbps TCP/IP stack for Vitis shells
Created
2020-11-11
15 commits to vitis_2022_1 branch, last one 10 months ago
VNx: Vitis Network Examples
Created
2020-07-28
287 commits to master branch, last one 6 months ago
Vitis Model Composer Examples and Tutorials
Created
2020-10-12
2,271 commits to 2024.2 branch, last one a day ago
Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
Created
2020-05-28
133 commits to master branch, last one 6 months ago
FPGA acceleration of arbitrary precision floating point computations.
Created
2021-10-01
153 commits to main branch, last one 2 years ago
High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
Created
2022-06-17
181 commits to main branch, last one 6 months ago